Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
16
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
6.
Processor and Architecture
6.1
ARM926EJ-S Processor
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RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
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Two Instruction Sets
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ARM High-performance 32-bit Instruction Set
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Thumb High Code Density 16-bit Instruction Set
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DSP Instruction Extensions
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5-Stage Pipeline Architecture:
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Instruction Fetch (F)
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Instruction
Decode (D)
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Execute (E)
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Data Memory (M)
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Register Write (W)
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32-KByte Data Cache, 32-KByte Instruction Cache
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Virtually-addressed 4-way Associative Cache
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Eight words per line
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Write-through and Write-back Operation
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Pseudo-random or Round-robin Replacement
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Write Buffer
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Main Write Buffer with 16-word Data Buffer and 4-address Buffer
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DCache Write-back Buffer with 8-word Entries and a Single Address Entry
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Software Control Drain
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Standard ARM v4 and v5 Memory Management Unit (MMU)
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Access Permission for Sections
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Access Permission for large pages and small pages can be specified separately for each quarter of the
page
page
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16 embedded domains
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Bus Interface Unit (BIU)
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Arbitrates and Schedules AHB Requests
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Separate Masters for both instruction and data access providing complete Matrix system flexibility
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Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
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On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
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TCM Interface