Data Sheet (AT91SAM9M10-G45-EK)Table of ContentsDescription11. Features22. Block Diagram33. Signal Description44. Package and Pinout114.1 Mechanical Overview of the 324-ball TFBGA Package114.2 324-ball TFBGA Package Pinout125. Power Considerations155.1 Power Supplies156. Processor and Architecture166.1 ARM926EJ-S Processor166.2 Bus Matrix176.2.1 Matrix Masters176.2.2 Matrix Slaves186.2.3 Masters to Slaves Access186.3 Peripheral DMA Controller (PDC)206.4 USB216.5 DMA Controller216.6 Debug and Test Features227. Memories237.1 Memory Mapping247.2 Embedded Memories247.2.1 Internal SRAM247.2.2 TCM Interface247.2.3 Internal ROM257.2.4 Boot Strategies257.2.4.1 BMS = 1, boot on embedded ROM257.2.4.2 BMS = 0, boot on external memory267.3 External Memories267.3.1 DDRSDRC0 Multi-port DDRSDR Controller267.3.2 External Bus Interface267.3.2.1 Static Memory Controller277.3.2.2 DDR2/SDR Controller277.3.2.3 NAND Flash Error Corrected Code Controller288. System Controller298.1 System Controller Mapping298.2 System Controller Block Diagram308.3 Reset Controller318.4 Shut Down Controller318.5 Clock Generator318.6 Slow Clock Selection328.6.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal328.6.2 Bypass the 32768 Hz Oscillator328.6.3 Switch from 32768 Hz Crystal to the Internal RC Oscillator328.7 Power Management Controller338.7.1 Main Application Modes348.7.1.1 Normal Mode348.7.1.2 USB HS and LP-DDR Mode348.7.1.3 No UDP HS, UHP FS and DDR2 Mode348.8 Periodic Interval Timer358.9 Watchdog Timer358.10 Real-Time Timer358.11 Real Time Clock358.12 General-Purpose Backup Registers358.13 Advanced Interrupt Controller358.14 Debug Unit368.15 Chip Identification368.16 PIO Controller369. Peripherals379.1 Peripheral Mapping379.2 Peripheral Identifiers379.3 Peripheral Interrupts and Clock Control389.3.1 System Interrupt389.3.2 External Interrupts389.4 Peripheral Signals Multiplexing on I/O Lines389.4.1 PIO Controller A Multiplexing399.4.2 PIO Controller B Multiplexing409.4.3 PIO Controller C Multiplexing419.4.4 PIO Controller D Multiplexing429.4.5 PIO Controller E Multiplexing4310. Embedded Peripherals4410.1 Serial Peripheral Interface (SPI)4410.2 Two Wire Interface (TWI)4410.3 Universal Synchronous Asynchronous Receiver Transmitter (USART)4410.4 Serial Synchronous Controller (SSC)4510.5 AC97 Controller4510.6 Timer Counter (TC)4510.7 Pulse Width Modulation Controller (PWM)4610.8 High Speed Multimedia Card Interface (MCI)4610.9 USB High Speed Host Port (UHPHS)4610.10 USB High Speed Device Port (UDPHS)4610.11 LCD Controller (LCDC)4610.12 Touch Screen Analog-to-Digital Converter (TSADC)4710.13 Ethernet 10/100 MAC (EMAC)4710.14 Image Sensor Interface (ISI)4710.15 8-channel DMA (DMA)4810.16 True Random Number Generator (TRNG)4810.17 Video Decoder (VDEC)4811. Mechanical Characteristics5011.1 Package Drawings5011.2 Soldering Profile5111.3 Marking5212. SAM9M10 Ordering Information53Revision History54Size: 345 KBPages: 55Language: EnglishOpen manual
Data Sheet (AT91SAM9M10-G45-EK)Table of ContentsSection 14Introduction41.1 Scope41.2 Applicable Documents5Section 26Kit Contents62.1 Deliverables62.2 Evaluation Board Specifications72.3 Electrostatic Warning7Section 38Power up83.1 Power Up the Board83.2 Battery83.3 DevStart83.4 Recovery Procedure93.5 Sample Code and Technical Support9Section 410Board Description104.1 Equipment on the Board104.1.1 Interfaces104.1.2 Board Interface Connection114.1.3 Push Button Switches114.1.4 Display LCD and LEDs124.2 Hardware Layout and Configuration124.2.1 Processor124.2.2 Clock Circuitry134.2.3 Reset Circuitry134.2.4 Memory134.2.5 Power Supplies164.2.6 Debug Interface194.2.7 Audio Stereo Interface244.2.8 TV-Out Extension264.2.9 Software Controlled LEDs274.2.10 Serial Peripheral Interface Controller (SPI)284.2.11 Two Wire Interface (TWI)284.2.12 SD/MMC Interface284.2.13 TFT LCD with Touch Panel294.2.14 Push Buttons314.2.15 Expansion Slot31Section 533Configuration335.1 JTAG/ICE Configuration335.2 ETHERNET Configuration335.3 Jumpers Configuration345.4 Miscellaneous Configuration Items355.5 PIO Configuration355.5.1 Peripheral Signals Multiplexing on I/O Lines355.5.2 Multiplexing on PIO Controller A (PIOA)355.5.3 Multiplexing on PIO Controller B (PIOB)375.5.4 Multiplexing on PIO Controller C (PIOC)385.5.5 Multiplexing on PIO Controller D (PIOD)395.5.6 Multiplexing on PIO Controller E (PIOE)40Section 641Connectors416.1 Power Supply416.2 RS232 Connector with RTS/CTS Handshake Support416.3 DBGU426.4 Ethernet436.5 USB Host436.6 USB Host/Device446.7 JTAG Debugging Connector446.8 SD/MMC- MCI0466.9 SD/MMC- MCI1476.10 AC97486.11 Image Sensor - ISI496.12 Video506.13 Display Devices506.13.1 TFT LCD506.14 LCD Extension51Section 753Schematics537.1 Schematics53Section 866Revision History668.1 Revision History66Size: 2.18 MBPages: 67Language: EnglishOpen manual
Data Sheet (AT91SAM9M10-G45-EK)Table of ContentsDescription11. Features22. Block Diagram33. Signal Description44. Package and Pinout114.1 Mechanical Overview of the 324-ball TFBGA Package114.2 324-ball TFBGA Package Pinout125. Power Considerations145.1 Power Supplies146. Memories156.1 Memory Mapping166.2 Embedded Memories166.2.1 Internal SRAM166.2.2 TCM Interface166.2.3 Internal ROM176.3 I/O Drive Selection and Delay Control176.3.1 I/O Drive Selection176.3.2 Delay Control177. System Controller197.1 System Controller Mapping197.2 System Controller Block Diagram207.3 Chip Identification217.4 Backup Section218. Peripherals228.1 Peripheral Mapping228.2 Peripheral Identifiers228.3 Peripheral Interrupts and Clock Control238.3.1 System Interrupt238.3.2 External Interrupts238.4 Peripheral Signals Multiplexing on I/O Lines238.4.1 PIO Controller A Multiplexing248.4.2 PIO Controller B Multiplexing258.4.3 PIO Controller C Multiplexing268.4.4 PIO Controller D Multiplexing278.4.5 PIO Controller E Multiplexing289. ARM926EJ-S Processor Overview299.1 Description299.2 Embedded Characteristics309.3 Block Diagram319.4 ARM9EJ-S Processor319.4.1 ARM9EJ-S Operating States319.4.2 Switching State329.4.3 Instruction Pipelines329.4.4 Memory Access329.4.5 Jazelle Technology329.4.6 ARM9EJ-S Operating Modes329.4.7 ARM9EJ-S Registers339.4.7.1 Status Registers349.4.7.2 Exceptions359.4.7.3 Exception Types and Priorities359.4.7.4 Exception Modes and Handling369.4.8 ARM Instruction Set Overview369.4.9 New ARM Instruction Set389.4.10 Thumb Instruction Set Overview389.5 CP15 Coprocessor409.5.1 CP15 Registers Access419.6 Memory Management Unit (MMU)429.6.1 Access Control Logic429.6.2 Translation Look-aside Buffer (TLB)429.6.3 Translation Table Walk Hardware439.6.4 MMU Faults439.7 Caches and Write Buffer449.7.1 Instruction Cache (ICache)449.7.2 Data Cache (DCache) and Write Buffer449.7.2.1 DCache449.7.2.2 Write Buffer459.7.2.3 Write-though Operation459.7.2.4 Write-back Operation459.8 Tightly-Coupled Memory Interface459.8.1 TCM Description459.8.2 Enabling and Disabling TCMs459.8.3 TCM Mapping469.9 Bus Interface Unit469.9.1 Supported Transfers469.9.2 Thumb Instruction Fetches469.9.3 Address Alignment4610. SAM9M10 Debug and Test4710.1 Description4710.2 Embedded Characteristics4710.3 Block Diagram4810.4 Application Examples4910.4.1 Debug Environment4910.4.2 Test Environment5010.5 Debug and Test Pin Description5010.6 Functional Description5110.6.1 Test Pin5110.6.2 EmbeddedICE5110.6.3 JTAG Signal Description5110.6.4 Debug Unit5110.6.5 IEEE 1149.1 JTAG Boundary Scan5210.6.6 JID Code Register5211. Boot Strategies5311.1 Boot Program5311.2 Flow Diagram5411.3 Device Initialization5511.3.1 Clock at Start Up5511.3.2 Initialization Sequence5511.4 NVM Boot5611.4.1 NVM Bootloader Program Description5611.4.2 Valid Code Detection5711.4.2.1 ARM Exception Vectors Check5711.4.2.2 boot.bin file check5811.4.3 NVM Bootloader Sequence5911.4.3.1 NAND Flash Boot5911.4.3.2 SD Card Boot6011.4.3.3 SPI Flash Boot6011.4.3.4 TWI EEPROM Boot6111.4.4 Hardware and Software Constraints6111.5 SAM-BA Monitor6211.5.1 Command List6311.5.2 DBGU Serial Port6411.5.2.1 Supported External Crystal/External Clocks6411.5.2.2 Xmodem Protocol6411.5.3 USB Device Port6511.5.3.1 Supported external crystal / external clocks6511.5.3.2 USB class6511.5.3.3 Enumeration Process6511.5.3.4 Communication Endpoints6612. Reset Controller (RSTC)6712.1 Description6712.2 Embedded Characteristics6712.3 Block Diagram6712.4 Functional Description6812.4.1 Reset Controller Overview6812.4.2 NRST Manager6812.4.2.1 NRST Signal or Interrupt6812.4.2.2 NRST External Reset Control6912.4.3 BMS Sampling6912.4.4 Reset States6912.4.4.1 General Reset6912.4.4.2 Wake-up Reset7112.4.4.3 User Reset7212.4.4.4 Software Reset7312.4.4.5 Watchdog Reset7412.4.5 Reset State Priorities7512.4.6 Reset Controller Status Register7612.5 Reset Controller (RSTC) User Interface7712.5.1 Reset Controller Control Register7812.5.2 Reset Controller Status Register7912.5.3 Reset Controller Mode Register8013. Real-time Timer (RTT)8113.1 Description8113.2 Embedded Characteristics8113.3 Block Diagram8113.4 Functional Description8113.5 Real-time Timer (RTT) User Interface8313.5.1 Real-time Timer Mode Register8413.5.2 Real-time Timer Alarm Register8513.5.3 Real-time Timer Value Register8513.5.4 Real-time Timer Status Register8614. Real-time Clock (RTC)8714.1 Description8714.2 Embedded Characteristics8714.3 Block Diagram8714.4 Product Dependencies8814.4.1 Power Management8814.4.2 Interrupt8814.5 Functional Description8814.5.1 Reference Clock8814.5.2 Timing8814.5.3 Alarm8814.5.4 Error Checking8914.5.5 Updating Time/Calendar8914.6 Real Time Clock (RTC) User Interface9114.6.1 RTC Control Register9214.6.2 RTC Mode Register9314.6.3 RTC Time Register9414.6.4 RTC Calendar Register9514.6.5 RTC Time Alarm Register9614.6.6 RTC Calendar Alarm Register9714.6.7 RTC Status Register9814.6.8 RTC Status Clear Command Register9914.6.9 RTC Interrupt Enable Register10014.6.10 RTC Interrupt Disable Register10114.6.11 RTC Interrupt Mask Register10214.6.12 RTC Valid Entry Register10315. Periodic Interval Timer (PIT)10515.1 Description10515.2 Embedded Characteristics10515.3 Block Diagram10515.4 Functional Description10615.5 Periodic Interval Timer (PIT) User Interface10715.5.1 Periodic Interval Timer Mode Register10815.5.2 Periodic Interval Timer Status Register10915.5.3 Periodic Interval Timer Value Register10915.5.4 Periodic Interval Timer Image Register11016. Watchdog Timer (WDT)11116.1 Description11116.2 Embedded Characteristics11116.3 Block Diagram11116.4 Functional Description11216.5 Watchdog Timer (WDT) User Interface11416.5.1 Watchdog Timer Control Register11516.5.2 Watchdog Timer Mode Register11616.5.3 Watchdog Timer Status Register11717. Shutdown Controller (SHDWC)11917.1 Description11917.2 Embedded Characteristics11917.3 Block Diagram11917.4 I/O Lines Description12017.5 Product Dependencies12017.5.1 Power Management12017.6 Functional Description12017.7 Shutdown Controller (SHDWC) User Interface12117.7.1 Shutdown Control Register12217.7.2 Shutdown Mode Register12317.7.3 Shutdown Status Register12418. General Purpose Backup Registers (GPBR)12518.1 Description12518.2 Embedded Characteristics12518.3 General Purpose Backup Registers (GPBR) User Interface12518.3.1 General Purpose Backup Register x12619. Bus Matrix (MATRIX)12719.1 Description12719.2 Embedded Characteristics12719.2.1 Matrix Masters12719.2.2 Matrix Slaves12819.2.3 Masters to Slaves Access12819.3 Memory Mapping13019.4 Special Bus Granting Mechanism13019.4.1 No Default Master13119.4.2 Last Access Master13119.4.3 Fixed Default Master13119.5 Arbitration13119.5.1 Arbitration Scheduling13219.5.1.1 Undefined Length Burst Arbitration13219.5.1.2 Slot Cycle Limit Arbitration13319.5.2 Arbitration Priority Scheme13319.5.2.1 Fixed Priority Arbitration13419.5.2.2 Round-Robin Arbitration13419.6 Write Protect Registers13519.7 Bus Matrix (MATRIX) User Interface13619.7.1 Bus Matrix Master Configuration Registers13819.7.2 Bus Matrix Slave Configuration Registers13919.7.3 Bus Matrix Priority Registers A For Slaves14119.7.4 Bus Matrix Priority Registers B For Slaves14219.7.5 Bus Matrix Master Remap Control Register14319.7.6 Chip Configuration User Interface14419.7.6.1 Bus Matrix TCM Configuration Register14519.7.6.2 Bus Matrix Video Mode Configuration Register14619.7.6.3 EBI Chip Select Assignment Register14719.7.7 Write Protect Mode Register14919.7.8 Write Protect Status Register15020. External Memories15120.1 DDRSDRC0 Multi-port DDRSDR Controller15220.1.1 Description15220.1.2 Embedded Characteristics15220.1.2.1 DDR2/LPDDR Controller15220.1.3 DDR2 Controller Block Diagram15320.1.4 I/O Lines Description15420.1.5 Product Dependencies15420.1.6 Implementation Example15420.1.6.1 2x8-bit DDR215520.2 External Bus Interface (EBI)15620.2.1 Description15620.2.2 Embedded Characteristics15620.2.2.1 External Bus Interface15620.2.2.2 Static Memory Controller15620.2.2.3 DDR2/SDR Controller15720.2.2.4 NAND Flash Error Corrected Code Controller15720.2.3 EBI Block Diagram15820.2.4 I/O Lines Description15920.2.5 Application Example16020.2.5.1 Hardware Interface16020.2.5.2 Connection Examples16220.2.6 Product Dependencies16320.2.6.1 I/O Lines16320.2.7 Functional Description16320.2.7.1 Bus Multiplexing16320.2.7.2 Pull-up Control16320.2.7.3 Static Memory Controller16320.2.7.4 DDR2SDRAM Controller16320.2.7.5 ECC Controller16320.2.7.6 CompactFlash Support16320.2.7.7 NAND Flash Support16720.2.8 Implementation Examples16820.2.8.1 2x8-bit DDR2 on EBI16920.2.8.2 16-bit LPDDR on EBI17020.2.8.3 16-bit SDRAM17120.2.8.4 2x16-bit SDRAM17220.2.8.5 8-bit NAND Flash17320.2.8.6 16-bit NAND Flash17420.2.8.7 NOR Flash on NCS017520.2.8.8 CompactFlash17620.2.8.9 CompactFlash True IDE17820.2.9 Programmable I/O Lines Power Supplies and Drive Levels17921. Static Memory Controller (SMC)18121.1 Description18121.2 I/O Lines Description18121.3 Multiplexed Signals18121.4 Application Example18221.4.1 Hardware Interface18221.5 Product Dependencies18221.5.1 I/O Lines18221.6 External Memory Mapping18321.7 Connection to External Devices18321.7.1 Data Bus Width18321.7.2 Byte Write or Byte Select Access18321.7.2.1 Byte Write Access18521.7.2.2 Byte Select Access18521.7.2.3 Signal Multiplexing18621.8 Standard Read and Write Protocols18721.8.1 Read Waveforms18721.8.1.1 NRD Waveform18721.8.1.2 NCS Waveform18721.8.1.3 Read Cycle18821.8.1.4 Null Delay Setup and Hold18821.8.1.5 Null Pulse18921.8.2 Read Mode18921.8.2.1 Read is Controlled by NRD (READ_MODE = 1):18921.8.2.2 Read is Controlled by NCS (READ_MODE = 0)18921.8.3 Write Waveforms19121.8.3.1 NWE Waveforms19121.8.3.2 NCS Waveforms19121.8.3.3 Write Cycle19121.8.3.4 Null Delay Setup and Hold19221.8.3.5 Null Pulse19221.8.4 Write Mode19221.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):19221.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)19321.8.5 Coding Timing Parameters19321.8.6 Reset Values of Timing Parameters19421.8.7 Usage Restriction19421.9 Automatic Wait States19421.9.1 Chip Select Wait States19421.9.2 Early Read Wait State19521.9.3 Reload User Configuration Wait State19721.9.3.1 User Procedure19721.9.3.2 Slow Clock Mode Transition19821.9.4 Read to Write Wait State19821.10 Data Float Wait States19921.10.1 READ_MODE19921.10.2 TDF Optimization Enabled (TDF_MODE = 1)20021.10.3 TDF Optimization Disabled (TDF_MODE = 0)20121.11 External Wait20321.11.1 Restriction20321.11.2 Frozen Mode20421.11.3 Ready Mode20621.11.4 NWAIT Latency and Read/Write Timings20821.12 Slow Clock Mode20921.12.1 Slow Clock Mode Waveforms20921.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode21021.13 Asynchronous Page Mode21221.13.1 Protocol and Timings in Page Mode21221.13.2 Byte Access Type in Page Mode21321.13.3 Page Mode Restriction21321.13.4 Sequential and Non-sequential Accesses21321.14 Programmable IO Delays21521.15 Static Memory Controller (SMC) User Interface21621.15.1 SMC Setup Register21721.15.2 SMC Pulse Register21821.15.3 SMC Cycle Register21921.15.4 SMC MODE Register22021.15.5 SMC DELAY I/O Register22222. DDR/SDR SDRAM Controller (DDRSDRC)22322.1 Description22322.2 Embedded Characteristics22422.3 DDRSDRC Module Diagram22522.4 Initialization Sequence22622.4.1 SDR-SDRAM Initialization22622.4.2 Low-power DDR1-SDRAM Initialization22722.4.3 DDR2-SDRAM Initialization22822.5 Functional Description23022.5.1 SDRAM Controller Write Cycle23022.5.2 SDRAM Controller Read Cycle23522.5.3 Refresh (Auto-refresh Command)23922.5.4 Power Management23922.5.4.1 Self Refresh Mode23922.5.4.2 Power-down Mode24222.5.4.3 Deep Power-down Mode24322.5.4.4 Reset Mode24422.5.5 Multi-port Functionality24522.5.6 Write Protected Registers24722.6 Software Interface/SDRAM Organization, Address Mapping24822.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width(1) and Four Banks24822.6.2 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width24922.7 Programmable IO Delays25022.8 DDR SDR SDRAM Controller (DDRSDRC) User Interface25122.8.1 DDRSDRC Mode Register25222.8.2 DDRSDRC Refresh Timer Register25322.8.3 DDRSDRC Configuration Register25422.8.4 DDRSDRC Timing Parameter 0 Register25722.8.5 DDRSDRC Timing Parameter 1 Register25922.8.6 DDRSDRC Timing Parameter 2 Register26022.8.7 DDRSDRC Low-power Register26122.8.8 DDRSDRC Memory Device Register26322.8.9 DDRSDRC DLL Register26422.8.10 DDRSDRC High Speed Register26522.8.11 DDRSDRC DELAY I/O Register26622.8.12 DDRSDRC Write Protect Mode Register26722.8.13 DDRSDRC Write Protect Status Register26823. Error Corrected Code Controller (ECC)26923.1 Description26923.2 Block Diagram26923.3 Functional Description26923.3.1 Write Access27023.3.2 Read Access27023.4 Error Corrected Code Controller (ECC) User Interface27423.4.1 ECC Control Register27523.4.2 ECC Mode Register27623.4.3 ECC Status Register 127723.4.4 ECC Status Register 228123.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes28523.5.1 ECC Parity Register 028523.5.2 ECC Parity Register 128623.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word28723.6.1 ECC Parity Register 028723.6.2 ECC Parity Register 128823.6.3 ECC Parity Register 228923.6.4 ECC Parity Register 329023.6.5 ECC Parity Register 429123.6.6 ECC Parity Register 529223.6.7 ECC Parity Register 629323.6.8 ECC Parity Register 729423.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word29523.7.1 ECC Parity Register 029523.7.2 ECC Parity Register 129623.7.3 ECC Parity Register 229723.7.4 ECC Parity Register 329823.7.5 ECC Parity Register 429923.7.6 ECC Parity Register 530023.7.7 ECC Parity Register 630123.7.8 ECC Parity Register 730223.7.9 ECC Parity Register 830323.7.10 ECC Parity Register 930423.7.11 ECC Parity Register 1030523.7.12 ECC Parity Register 1130623.7.13 ECC Parity Register 1230723.7.14 ECC Parity Register 1330823.7.15 ECC Parity Register 1430923.7.16 ECC Parity Register 1531024. Peripheral DMA Controller (PDC)31124.1 Description31124.2 Embedded Characteristics31124.3 Block Diagram31224.4 Functional Description31324.4.1 Configuration31324.4.2 Memory Pointers31324.4.3 Transfer Counters31324.4.4 Data Transfers31424.4.5 PDC Flags and Peripheral Status Register31424.4.5.1 Receive Transfer End31424.4.5.2 Transmit Transfer End31424.4.5.3 Receive Buffer Full31424.4.5.4 Transmit Buffer Empty31424.5 Peripheral DMA Controller (PDC) User Interface31524.5.1 Receive Pointer Register31624.5.2 Receive Counter Register31624.5.3 Transmit Pointer Register31724.5.4 Transmit Counter Register31724.5.5 Receive Next Pointer Register31824.5.6 Receive Next Counter Register31824.5.7 Transmit Next Pointer Register31924.5.8 Transmit Next Counter Register31924.5.9 Transfer Control Register32024.5.10 Transfer Status Register32125. Clock Generator32325.1 Description32325.2 Embedded Characteristics32325.3 Slow Clock Crystal Oscillator32425.4 Slow Clock RC Oscillator32425.5 Slow Clock Selection32425.5.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal32525.5.2 Bypass the 32768 Hz Oscillator32525.5.3 Switch from 32768 Hz Crystal to the Internal RC oscillator32525.5.4 Slow Clock Configuration Register32625.6 Main Oscillator32725.6.1 Main Oscillator Connections32725.6.2 Main Oscillator Startup Time32725.6.3 Main Oscillator Control32725.6.4 Main Oscillator Bypass32825.7 Divider and PLLA Block32825.7.1 Divider and Phase Lock Loop Programming32825.8 UTMI Bias and Phase Lock Loop Programming32926. Power Management Controller (PMC)33026.1 Description33026.2 Embedded Characteristics33026.2.1 Main Application Modes33126.2.1.1 Normal Mode33126.2.1.2 USB HS and LP-DDR Mode33126.2.1.3 No UDP HS, UHP FS and DDR2 Mode33226.3 Master Clock Controller33226.4 Processor Clock Controller33226.5 USB Device and Host clocks33326.6 LP-DDR/DDR2 Clock33326.7 Peripheral Clock Controller33326.8 Programmable Clock Output Controller33426.9 Programming Sequence33426.10 Clock Switching Details33826.10.1 Master Clock Switching Timings33826.10.2 Clock Switching Waveforms33826.11 Power Management Controller (PMC) User Interface34126.11.1 PMC System Clock Enable Register34226.11.2 PMC System Clock Disable Register34326.11.3 PMC System Clock Status Register34426.11.4 PMC Peripheral Clock Enable Register34526.11.5 PMC Peripheral Clock Disable Register34626.11.6 PMC Peripheral Clock Status Register34726.11.7 PMC UTMI Clock Configuration Register34826.11.8 PMC Clock Generator Main Oscillator Register34926.11.9 PMC Clock Generator Main Clock Frequency Register35026.11.10 PMC Clock Generator PLLA Register35126.11.11 PMC USB Clock Register35226.11.12 PMC Master Clock Register35326.11.13 PMC Programmable Clock Register35526.11.14 PMC Interrupt Enable Register35626.11.15 PMC Interrupt Disable Register35726.11.16 PMC Status Register35826.11.17 PMC Interrupt Mask Register35926.11.18 PLL Charge Pump Current Register36027. Serial Peripheral Interface (SPI)36127.1 Description36127.2 Embedded Characteristics36127.3 Block Diagram36227.4 Application Block Diagram36327.5 Signal Description36427.6 Product Dependencies36427.6.1 I/O Lines36427.6.2 Power Management36427.6.3 Interrupt36527.6.4 Peripheral DMA Controller (PDMA) Direct Memory Access Controller (DMAC)36527.7 Functional Description36527.7.1 Modes of Operation36527.7.2 Data Transfer36527.7.3 Master Mode Operations36727.7.3.1 Master Mode Block Diagram36827.7.3.2 Master Mode Flow Diagram36927.7.3.3 Clock Generation37127.7.3.4 Transfer Delays37127.7.3.5 Peripheral Selection37127.7.3.6 SPI Peripheral DMA Controller (PDC)37227.7.3.7 Transfer Size37227.7.3.8 SPI Direct Access Memory Controller (DMAC)37327.7.3.9 Peripheral Chip Select Decoding37327.7.3.10 Peripheral Deselection without PDCDMAC37427.7.3.11 Peripheral Deselection with PDC37427.7.3.12 Peripheral Deselection with DMAC37527.7.3.13 Mode Fault Detection37527.7.4 SPI Slave Mode37627.8 Serial Peripheral Interface (SPI) User Interface37727.8.1 SPI Control Register37827.8.2 SPI Mode Register37927.8.3 SPI Receive Data Register38127.8.4 SPI Transmit Data Register38227.8.5 SPI Status Register38327.8.6 SPI Interrupt Enable Register38527.8.7 SPI Interrupt Disable Register38627.8.8 SPI Interrupt Mask Register38727.8.9 SPI Chip Select Register38828. Advanced Interrupt Controller (AIC)39128.1 Description39128.2 Embedded Characteristics39128.3 Block Diagram39228.4 Application Block Diagram39228.5 AIC Detailed Block Diagram39228.6 I/O Line Description39328.7 Product Dependencies39328.7.1 I/O Lines39328.7.2 Power Management39328.7.3 Interrupt Sources39328.8 Functional Description39428.8.1 Interrupt Source Control39428.8.1.1 Interrupt Source Mode39428.8.1.2 Interrupt Source Enabling39428.8.1.3 Interrupt Clearing and Setting39428.8.1.4 Interrupt Status39428.8.1.5 Internal Interrupt Source Input Stage39528.8.1.6 External Interrupt Source Input Stage39528.8.2 Interrupt Latencies39628.8.2.1 External Interrupt Edge Triggered Source39628.8.2.2 External Interrupt Level Sensitive Source39628.8.2.3 Internal Interrupt Edge Triggered Source39728.8.2.4 Internal Interrupt Level Sensitive Source39728.8.3 Normal Interrupt39728.8.3.1 Priority Controller39728.8.3.2 Interrupt Nesting39828.8.3.3 Interrupt Vectoring39828.8.3.4 Interrupt Handlers39828.8.4 Fast Interrupt39928.8.4.1 Fast Interrupt Source39928.8.4.2 Fast Interrupt Control39928.8.4.3 Fast Interrupt Vectoring40028.8.4.4 Fast Interrupt Handlers40028.8.4.5 Fast Forcing40128.8.5 Protect Mode40228.8.6 Spurious Interrupt40228.8.7 General Interrupt Mask40328.9 Advanced Interrupt Controller (AIC) User Interface40428.9.1 Base Address40428.9.2 AIC Source Mode Register40528.9.3 AIC Source Vector Register40628.9.4 AIC Interrupt Vector Register40628.9.5 AIC FIQ Register40728.9.6 AIC Interrupt Status Register40728.9.7 AIC Interrupt Pending Register40828.9.8 AIC Interrupt Mask Register40828.9.9 AIC Core Interrupt Status Register40928.9.10 AIC Interrupt Enable Command Register40928.9.11 AIC Interrupt Disable Command Register41028.9.12 AIC Interrupt Clear Command Register41028.9.13 AIC Interrupt Set Command Register41128.9.14 AIC End of Interrupt Command Register41128.9.15 AIC Spurious Interrupt Vector Register41228.9.16 AIC Debug Control Register41228.9.17 AIC Fast Forcing Enable Register41328.9.18 AIC Fast Forcing Disable Register41328.9.19 AIC Fast Forcing Status Register41429. Debug Unit (DBGU)41529.1 Description41529.2 Embedded Characteristics41529.3 Block Diagram41629.4 Product Dependencies41729.4.1 I/O Lines41729.4.2 Power Management41729.4.3 Interrupt Source41729.5 UART Operations41729.5.1 Baud Rate Generator41729.5.2 Receiver41829.5.2.1 Receiver Reset, Enable and Disable41829.5.2.2 Start Detection and Data Sampling41829.5.2.3 Receiver Ready41929.5.2.4 Receiver Overrun41929.5.2.5 Parity Error41929.5.2.6 Receiver Framing Error42029.5.3 Transmitter42029.5.3.1 Transmitter Reset, Enable and Disable42029.5.3.2 Transmit Format42029.5.3.3 Transmitter Control42129.5.4 Peripheral Data Controller42129.5.5 Test Modes42129.5.6 Debug Communication Channel Support42229.5.7 Chip Identifier42329.5.8 ICE Access Prevention42329.6 Debug Unit (DBGU) User Interface42429.6.1 Debug Unit Control Register42529.6.2 Debug Unit Mode Register42629.6.3 Debug Unit Interrupt Enable Register42729.6.4 Debug Unit Interrupt Disable Register42829.6.5 Debug Unit Interrupt Mask Register42929.6.6 Debug Unit Status Register43029.6.7 Debug Unit Receiver Holding Register43229.6.8 Debug Unit Transmit Holding Register43229.6.9 Debug Unit Baud Rate Generator Register43329.6.10 Debug Unit Chip ID Register43429.6.11 Debug Unit Chip ID Extension Register43729.6.12 Debug Unit Force NTRST Register43830. Parallel Input/Output Controller (PIO)43930.1 Description43930.2 Block Diagram44030.3 Product Dependencies44130.3.1 Pin Multiplexing44130.3.2 External Interrupt Lines44130.3.3 Power Management44130.3.4 Interrupt Generation44130.4 Functional Description44230.4.1 Pull-up Resistor Control44330.4.2 I/O Line or Peripheral Function Selection44330.4.3 Peripheral A or B Selection44330.4.4 Output Control44330.4.5 Synchronous Data Output44430.4.6 Multi Drive Control (Open Drain)44430.4.7 Output Line Timings44430.4.8 Inputs44430.4.9 Input Glitch Filtering44530.4.10 Input Change Interrupt44530.4.11 Write Protected Registers44630.4.12 Programmable I/O Delays44730.5 I/O Lines Programming Example44830.6 Parallel Input/Output Controller (PIO) User Interface44930.6.1 PIO Enable Register45130.6.2 PIO Disable Register45130.6.3 PIO Status Register45230.6.4 PIO Output Enable Register45230.6.5 PIO Output Disable Register45330.6.6 PIO Output Status Register45330.6.7 PIO Input Filter Enable Register45430.6.8 PIO Input Filter Disable Register45430.6.9 PIO Input Filter Status Register45530.6.10 PIO Set Output Data Register45530.6.11 PIO Clear Output Data Register45630.6.12 PIO Output Data Status Register45630.6.13 PIO Pin Data Status Register45730.6.14 PIO Interrupt Enable Register45730.6.15 PIO Interrupt Disable Register45830.6.16 PIO Interrupt Mask Register45830.6.17 PIO Interrupt Status Register45930.6.18 PIO Multi-driver Enable Register45930.6.19 PIO Multi-driver Disable Register46030.6.20 PIO Multi-driver Status Register46030.6.21 PIO Pull Up Disable Register46130.6.22 PIO Pull Up Enable Register46130.6.23 PIO Pull Up Status Register46230.6.24 PIO Peripheral A Select Register46230.6.25 PIO Peripheral B Select Register46330.6.26 PIO Peripheral A B Status Register46330.6.27 PIO Output Write Enable Register46430.6.28 PIO Output Write Disable Register46430.6.29 PIO Output Write Status Register46530.6.30 PIO I/O Delay Register46630.6.31 PIO Write Protect Mode Register46730.6.32 PIO Write Protect Status Register46831. Universal Synchronous Asynchronous Receiver Transmitter (USART)46931.1 Description46931.2 Embedded Characteristics46931.3 Block Diagram47031.4 Application Block Diagram47131.5 I/O Lines Description47131.6 Product Dependencies47231.6.1 I/O Lines47231.6.2 Power Management47231.6.3 Interrupt47331.7 Functional Description47331.7.1 Baud Rate Generator47531.7.1.1 Baud Rate in Asynchronous Mode47531.7.1.2 Baud Rate Calculation Example47631.7.1.3 Fractional Baud Rate in Asynchronous Mode47631.7.1.4 Baud Rate in Synchronous Mode or SPI Mode47731.7.1.5 Baud Rate in ISO 7816 Mode47731.7.2 Receiver and Transmitter Control47931.7.3 Synchronous and Asynchronous Modes47931.7.3.1 Transmitter Operations47931.7.3.2 Manchester Encoder48031.7.3.3 Drift Compensation48231.7.3.4 Asynchronous Receiver48231.7.3.5 Manchester Decoder48431.7.3.6 Radio Interface: Manchester Encoded USART Application48531.7.3.7 Synchronous Receiver48731.7.3.8 Receiver Operations48731.7.3.9 Parity48931.7.3.10 Multidrop Mode49031.7.3.11 Transmitter Timeguard49031.7.3.12 Receiver Time-out49131.7.3.13 Framing Error49231.7.3.14 Transmit Break49331.7.3.15 Receive Break49431.7.3.16 Hardware Handshaking49431.7.4 ISO7816 Mode49531.7.4.1 ISO7816 Mode Overview49531.7.4.2 Protocol T = 049631.7.4.3 Receive Error Counter49631.7.4.4 Receive NACK Inhibit49631.7.4.5 Transmit Character Repetition49731.7.4.6 Disable Successive Receive NACK49731.7.4.7 Protocol T = 149731.7.5 IrDA Mode49731.7.5.1 IrDA Modulation49831.7.5.2 IrDA Baud Rate49831.7.5.3 IrDA Demodulator49931.7.6 RS485 Mode50031.7.7 SPI Mode50031.7.7.1 Modes of Operation50131.7.7.2 Baud Rate50131.7.7.3 Data Transfer50231.7.7.4 Receiver and Transmitter Control50331.7.7.5 Character Transmission50431.7.7.6 Character Reception50431.7.7.7 Receiver Timeout50431.7.8 LIN Mode50531.7.8.1 Modes of operation50531.7.8.2 Receiver and Transmitter Control50531.7.8.3 Character Transmission50531.7.8.4 Character Reception50531.7.8.5 Header Transmission (Master Node Configuration)50631.7.8.6 Header Reception (Slave Node Configuration)50731.7.8.7 Slave Node Synchronization50831.7.8.8 Identifier Parity50931.7.8.9 Node Action51031.7.8.10 Response Data Length51131.7.8.11 Checksum51131.7.8.12 Frame Slot Mode51231.7.8.13 LIN Errors51331.7.8.14 Bit Error51331.7.8.15 Inconsistent Synch Field Error51331.7.8.16 Parity Error51331.7.8.17 Checksum Error51331.7.8.18 Slave Not Responding Error51331.7.8.19 LIN Frame Handling51331.7.8.20 Master Node Configuration51331.7.8.21 Slave Node Configuration51531.7.8.22 LIN Frame Handling With The Peripheral DMA Controller51631.7.8.23 Master Node Configuration51731.7.8.24 Slave Node Configuration51831.7.8.25 Wake-up Request51831.7.8.26 Bus Idle Time-out51931.7.9 Test Modes51931.7.9.1 Normal Mode51931.7.9.2 Automatic Echo Mode51931.7.9.3 Local Loopback Mode52031.7.9.4 Remote Loopback Mode52031.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface52131.8.1 USART Control Register52231.8.2 USART Mode Register52531.8.3 USART Interrupt Enable Register52931.8.4 USART Interrupt Disable Register53131.8.5 USART Interrupt Mask Register53331.8.6 USART Channel Status Register53531.8.7 USART Receive Holding Register53831.8.8 USART Transmit Holding Register53931.8.9 USART Baud Rate Generator Register54031.8.10 USART Receiver Time-out Register54131.8.11 USART Transmitter Timeguard Register54231.8.12 USART FI DI RATIO Register54331.8.13 USART Number of Errors Register54431.8.14 USART IrDA FILTER Register54531.8.15 USART Manchester Configuration Register54631.8.16 USART3 LIN Mode Register54831.8.17 USART3 LIN Identifier Register55032. Two-wire Interface (TWI)55132.1 Description55132.2 Embedded Characteristics55132.3 List of Abbreviations55232.4 Block Diagram55232.5 Application Block Diagram55332.5.1 I/O Lines Description55332.6 Product Dependencies55332.6.1 I/O Lines55332.6.2 Power Management55332.6.3 Interrupt55432.7 Functional Description55432.7.1 Transfer Format55432.7.2 Modes of Operation55432.8 Master Mode55532.8.1 Definition55532.8.2 Application Block Diagram55532.8.3 Programming Master Mode55532.8.4 Master Transmitter Mode55532.8.5 Master Receiver Mode55732.8.6 Internal Address55832.8.6.1 7-bit Slave Addressing55832.8.6.2 10-bit Slave Addressing55932.8.7 SMBUS Quick Command (Master Mode Only)56032.8.8 Read-write Flowcharts56032.9 Multi-master Mode56732.9.1 Definition56732.9.2 Different Multi-master Modes56732.9.2.1 TWI as Master Only56732.9.2.2 TWI as Master or Slave56732.10 Slave Mode57032.10.1 Definition57032.10.2 Application Block Diagram57032.10.3 Programming Slave Mode57032.10.4 Receiving Data57032.10.4.1 Read Sequence57032.10.4.2 Write Sequence57132.10.4.3 Clock Synchronization Sequence57132.10.4.4 General Call57132.10.5 Data Transfer57232.10.5.1 Read Operation57232.10.5.2 Write Operation57232.10.5.3 General Call57332.10.5.4 Clock Synchronization57432.10.5.5 Clock Synchronization in Read Mode57432.10.5.6 Clock Synchronization in Write Mode57532.10.5.7 Reversal after a Repeated Start57632.10.5.8 Reversal of Read to Write57632.10.5.9 Reversal of Write to Read57632.10.6 Read Write Flowcharts57732.11 Two-wire Interface (TWI) User Interface57832.11.1 TWI Control Register57932.11.2 TWI Master Mode Register58132.11.3 TWI Slave Mode Register58232.11.4 TWI Internal Address Register58332.11.5 TWI Clock Waveform Generator Register58432.11.6 TWI Status Register58532.11.7 TWI Interrupt Enable Register58832.11.8 TWI Interrupt Disable Register58932.11.9 TWI Interrupt Mask Register59032.11.10 TWI Receive Holding Register59132.11.11 TWI Transmit Holding Register59233. Synchronous Serial Controller (SSC)59333.1 Description59333.2 Embedded Characteristics59333.3 Block Diagram59433.4 Application Block Diagram59533.5 Pin Name List59633.6 Product Dependencies59633.6.1 I/O Lines59633.6.2 Power Management59633.6.3 Interrupt59633.7 Functional Description59833.7.1 Clock Management59933.7.1.1 Clock Divider60033.7.1.2 Transmitter Clock Management60033.7.1.3 Receiver Clock Management60133.7.1.4 Serial Clock Ratio Considerations60133.7.2 Transmitter Operations60233.7.3 Receiver Operations60233.7.4 Start60333.7.5 Frame Sync60533.7.5.1 Frame Sync Data60533.7.5.2 Frame Sync Edge Detection60533.7.6 Receive Compare Modes60533.7.6.1 Compare Functions60533.7.7 Data Format60633.7.8 Loop Mode60833.7.9 Interrupt60833.8 SSC Application Examples61033.9 Synchronous Serial Controller (SSC) User Interface61233.9.1 SSC Control Register61333.9.2 SSC Clock Mode Register61433.9.3 SSC Receive Clock Mode Register61533.9.4 SSC Receive Frame Mode Register61733.9.5 SSC Transmit Clock Mode Register61933.9.6 SSC Transmit Frame Mode Register62133.9.7 SSC Receive Holding Register62333.9.8 SSC Transmit Holding Register62333.9.9 SSC Receive Synchronization Holding Register62433.9.10 SSC Transmit Synchronization Holding Register62433.9.11 SSC Receive Compare 0 Register62533.9.12 SSC Receive Compare 1 Register62633.9.13 SSC Status Register62733.9.14 SSC Interrupt Enable Register62933.9.15 SSC Interrupt Disable Register63133.9.16 SSC Interrupt Mask Register63334. Timer Counter (TC)63534.1 Description63534.2 Embedded Characteristics63534.3 Block Diagram63634.4 Pin Name List63734.5 Product Dependencies63734.5.1 I/O Lines63734.5.2 Power Management63734.5.3 Interrupt63734.6 Functional Description63834.6.1 TC Description63834.6.2 16-bit Counter63834.6.3 Clock Selection63834.6.4 Clock Control64034.6.5 TC Operating Modes64034.6.6 Trigger64034.6.7 Capture Operating Mode64134.6.8 Capture Registers A and B64134.6.9 Trigger Conditions64134.6.10 Waveform Operating Mode64334.6.11 Waveform Selection64334.6.11.1 WAVSEL = 0064534.6.11.2 WAVSEL = 1064634.6.11.3 WAVSEL = 0164734.6.11.4 WAVSEL = 1164834.6.12 External Event/Trigger Conditions64934.6.13 Output Controller64934.7 Timer Counter (TC) User Interface65034.7.1 TC Block Control Register65134.7.2 TC Block Mode Register65234.7.3 TC Channel Control Register65334.7.4 TC Channel Mode Register: Capture Mode65434.7.5 TC Channel Mode Register: Waveform Mode65634.7.6 TC Counter Value Register66034.7.7 TC Register A66034.7.8 TC Register B66134.7.9 TC Register C66134.7.10 TC Status Register66234.7.11 TC Interrupt Enable Register66434.7.12 TC Interrupt Disable Register66534.7.13 TC Interrupt Mask Register66635. High Speed MultiMedia Card Interface (HSMCI)66735.1 Description66735.2 Embedded Characteristics66735.3 Block Diagram66835.4 Application Block Diagram66935.5 Pin Name List66935.6 Product Dependencies67035.6.1 I/O Lines67035.6.2 Power Management67035.6.3 Interrupt67035.7 Bus Topology67135.8 High Speed MultiMedia Card Operations67335.8.1 Command - Response Operation67435.8.2 Data Transfer Operation67635.8.3 Read Operation67635.8.4 Write Operation67835.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller68135.8.6 READ_SINGLE_BLOCK Operation using DMA Controller68235.8.6.1 Block Length is Multiple of 468235.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)68335.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)68435.8.7 WRITE_MULTIPLE_BLOCK68535.8.7.1 One Block per Descriptor68535.8.8 READ_MULTIPLE_BLOCK68635.8.8.1 Block Length is a Multiple of 468635.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)68735.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)68935.9 SD/SDIO Card Operation69035.9.1 SDIO Data Transfer Type69135.9.2 SDIO Interrupts69135.10 CE-ATA Operation69135.10.1 Executing an ATA Polling Command69135.10.2 Executing an ATA Interrupt Command69135.10.3 Aborting an ATA Command69135.10.4 CE-ATA Error Recovery69235.11 HSMCI Boot Operation Mode69235.11.1 Boot Procedure, Processor Mode69235.11.2 Boot Procedure, DMA Mode69335.12 HSMCI Transfer Done Timings69435.12.1 Definition69435.12.2 Read Access69435.12.3 Write Access69535.13 MultiMedia Card Interface (MCI) User Interface69635.13.1 HSMCI Control Register69735.13.2 HSMCI Mode Register69835.13.3 HSMCI Data Timeout Register70035.13.4 HSMCI SDCard/SDIO Register70135.13.5 HSMCI Argument Register70235.13.6 HSMCI Command Register70335.13.7 HSMCI Block Register70635.13.8 HSMCI Completion Signal Timeout Register70735.13.9 HSMCI Response Register70835.13.10 HSMCI Receive Data Register70835.13.11 HSMCI Transmit Data Register70935.13.12 HSMCI Status Register71035.13.13 HSMCI Interrupt Enable Register71435.13.14 HSMCI Interrupt Disable Register71635.13.15 HSMCI Interrupt Mask Register71835.13.16 HSMCI DMA Configuration Register72035.13.17 HSMCI Configuration Register72135.13.18 HSMCI Write Protect Mode Register72235.13.19 HSMCI Write Protect Status Register72335.13.20 HSMCI FIFO Memory Aperture72436. Ethernet MAC 10/100 (EMAC)72536.1 Description72536.2 Embedded Characteristics72536.3 Block Diagram72636.4 Functional Description72736.4.1 Clock72736.4.2 Memory Interface72736.4.2.1 FIFO72736.4.2.2 Receive Buffers72836.4.2.3 Transmit Buffer73036.4.3 Transmit Block73136.4.4 Pause Frame Support73236.4.5 Receive Block73236.4.6 Address Checking Block73336.4.7 Broadcast Address73436.4.8 Hash Addressing73436.4.9 Copy All Frames (or Promiscuous Mode)73436.4.10 Type ID Checking73436.4.11 VLAN Support73536.4.12 Wake-on-LAN Support73536.4.13 PHY Maintenance73636.4.14 Media Independent Interface73636.4.14.1 RMII Transmit and Receive Operation73736.5 Programming Interface73836.5.1 Initialization73836.5.1.1 Configuration73836.5.1.2 Receive Buffer List73836.5.1.3 Transmit Buffer List73936.5.1.4 Address Matching73936.5.1.5 Interrupts73936.5.1.6 Transmitting Frames73936.5.1.7 Receiving Frames73936.6 Ethernet MAC 10/100 (EMAC) User Interface74136.6.1 Network Control Register74336.6.2 Network Configuration Register74536.6.3 Network Status Register74736.6.4 Transmit Status Register74836.6.5 Receive Buffer Queue Pointer Register74936.6.6 Transmit Buffer Queue Pointer Register75036.6.7 Receive Status Register75136.6.8 Interrupt Status Register75236.6.9 Interrupt Enable Register75436.6.10 Interrupt Disable Register75636.6.11 Interrupt Mask Register75836.6.12 PHY Maintenance Register76036.6.13 Pause Time Register76136.6.14 Hash Register Bottom76236.6.15 Hash Register Top76236.6.16 Specific Address 1 Bottom Register76336.6.17 Specific Address 1 Top Register76336.6.18 Specific Address 2 Bottom Register76436.6.19 Specific Address 2 Top Register76436.6.20 Specific Address 3 Bottom Register76536.6.21 Specific Address 3 Top Register76536.6.22 Specific Address 4 Bottom Register76636.6.23 Specific Address 4 Top Register76636.6.24 Type ID Checking Register76736.6.25 User Input/Output Register76736.6.26 Wake-on-LAN Register76836.6.27 EMAC Statistic Registers76936.6.27.1 Pause Frames Received Register76936.6.27.2 Frames Transmitted OK Register76936.6.27.3 Single Collision Frames Register77036.6.27.4 Multicollision Frames Register77036.6.27.5 Frames Received OK Register77136.6.27.6 Frames Check Sequence Errors Register77136.6.27.7 Alignment Errors Register77236.6.27.8 Deferred Transmission Frames Register77236.6.27.9 Late Collisions Register77336.6.27.10 Excessive Collisions Register77336.6.27.11 Transmit Underrun Errors Register77436.6.27.12 Carrier Sense Errors Register77436.6.27.13 Receive Resource Errors Register77536.6.27.14 Receive Overrun Errors Register77536.6.27.15 Receive Symbol Errors Register77636.6.27.16 Excessive Length Errors Register77636.6.27.17 Receive Jabbers Register77736.6.27.18 Undersize Frames Register77736.6.27.19 SQE Test Errors Register77836.6.27.20 Received Length Field Mismatch Register77837. USB High Speed Host Port (UHPHS)77937.1 Description77937.2 Embedded Characteristics77937.2.1 EHCI77937.2.2 OHCI77937.3 Block Diagram78137.4 Product Dependencies78237.4.1 I/O Lines78237.5 I/O Lines78237.5.1 Power Management78237.5.2 Interrupt78337.6 Typical Connection78438. USB High Speed Device Port (UDPHS)78538.1 Description78538.2 Embedded Characteristics78538.3 Block Diagram78738.4 Typical Connection78838.5 Functional Description78938.5.1 USB V2.0 High Speed Device Port Introduction78938.5.2 USB V2.0 High Speed Transfer Types78938.5.3 USB Transfer Event Definitions78938.5.4 USB V2.0 High Speed BUS Transactions79038.5.5 Endpoint Configuration79038.5.6 Transfer With DMA79338.5.7 Transfer Without DMA79438.5.8 Handling Transactions with USB V2.0 Device Peripheral79438.5.8.1 Setup Transaction79438.5.8.2 NYET79538.5.8.3 Data IN79538.5.8.4 Bulk IN or Interrupt IN79538.5.8.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)79538.5.8.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)79638.5.8.7 Isochronous IN80038.5.8.8 High Bandwidth Isochronous Endpoint Handling: IN Example80038.5.8.9 Data OUT80138.5.8.10 Bulk OUT or Interrupt OUT80138.5.8.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)80138.5.8.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)80138.5.8.13 High Bandwidth Isochronous Endpoint OUT80338.5.8.14 Isochronous Endpoint Handling: OUT Example80438.5.8.15 STALL80538.5.9 Speed Identification80638.5.10 USB V2.0 High Speed Global Interrupt80638.5.11 Endpoint Interrupts80638.5.12 Power Modes80838.5.12.1 Controlling Device States80838.5.12.2 Not Powered State80938.5.12.3 Entering Attached State80938.5.12.4 From Powered State to Default State (Reset)80938.5.12.5 From Default State to Address State (Address Assigned)80938.5.12.6 From Address State to Configured State (Device Configured)80938.5.12.7 Entering Suspend State (Bus Activity)80938.5.12.8 Receiving a Host Resume81038.5.12.9 Sending an External Resume81038.5.13 Test Mode81138.6 USB High Speed Device Port (UDPHS) User Interface81238.6.1 UDPHS Control Register81338.6.2 UDPHS Frame Number Register81538.6.3 UDPHS Interrupt Enable Register81638.6.4 UDPHS Interrupt Status Register81938.6.5 UDPHS Clear Interrupt Register82138.6.6 UDPHS Endpoints Reset Register82238.6.7 UDPHS Test Register82338.6.8 UDPHS Name1 Register82538.6.9 UDPHS Name2 Register82638.6.10 UDPHS Features Register82738.6.11 UDPHS Endpoint Configuration Register82938.6.12 UDPHS Endpoint Control Enable Register83138.6.13 UDPHS Endpoint Control Disable Register83338.6.14 UDPHS Endpoint Control Register83538.6.15 UDPHS Endpoint Set Status Register83838.6.16 UDPHS Endpoint Clear Status Register83938.6.17 UDPHS Endpoint Status Register84138.6.18 UDPHS DMA Channel Transfer Descriptor84638.6.19 UDPHS DMA Next Descriptor Address Register84738.6.20 UDPHS DMA Channel Address Register84838.6.21 UDPHS DMA Channel Control Register84938.6.22 UDPHS DMA Channel Status Register85139. Image Sensor Interface (ISI)85339.1 Description85339.2 Embedded Characteristics85339.3 Block Diagram85439.4 Functional Description85539.4.1 Data Timing85539.4.2 Data Ordering85639.4.3 Clocks85739.4.4 Preview Path85839.4.4.1 Scaling, Decimation (Subsampling)85839.4.4.2 Color Space Conversion85939.4.4.3 Memory Interface86039.4.4.4 FIFO and DMA Features86039.4.4.5 Example86039.4.5 Codec Path86239.4.5.1 Color Space Conversion86239.4.5.2 Memory Interface86239.4.5.3 DMA Features86239.5 Image Sensor Interface (ISI) User Interface86339.5.1 ISI Configuration 1 Register86439.5.2 ISI Configuration 2 Register86639.5.3 ISI Preview Register86839.5.4 ISI Preview Decimation Factor Register86939.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register87039.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register87139.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register87239.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register87339.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register87439.5.10 ISI Control Register87539.5.11 ISI Status Register87639.5.12 ISI Interrupt Enable Register87839.5.13 ISI Interrupt Disable Register87939.5.14 ISI Interrupt Mask Register88039.5.15 DMA Channel Enable Register88239.5.16 DMA Channel Disable Register88339.5.17 DMA Channel Status Register88439.5.18 DMA Preview Base Address Register88539.5.19 DMA Preview Control Register88639.5.20 DMA Preview Descriptor Address Register88739.5.21 DMA Codec Base Address Register88839.5.22 DMA Codec Control Register88939.5.23 DMA Codec Descriptor Address Register89039.5.24 ISI Write Protection Control89139.5.25 ISI Write Protection Status89240. Touch Screen ADC Controller (TSADCC)89340.1 Description89340.2 Embedded Characteristics89340.3 Block Diagram89440.4 Signal Description89540.5 Product Dependencies89540.5.1 Power Management89540.5.2 Interrupt Sources89540.5.3 Analog Inputs89540.5.4 I/O Lines89540.5.5 Conversion Performances89540.6 Analog-to-digital Converter Functional Description89640.6.1 ADC Resolution89640.6.2 ADC Clock89640.6.3 Sleep Mode89640.6.4 Startup Time89640.6.5 Sample and Hold Time89740.7 Touch Screen89740.7.1 Resistive Touch Screen Principles89740.7.2 Position Measurement Method89840.7.3 Pressure Measurement Method89940.7.4 Pen Detect Method90040.8 Conversion Results90240.9 Conversion Triggers90440.10 Operating Modes90440.10.1 ADC Mode90440.10.2 Touch Screen Mode90540.10.3 Interleaved Mode90640.10.4 Manual Mode91040.11 Touch Screen ADC Controller (TSADCC) User Interface91140.11.1 TSADCC Control Register91240.11.2 TSADCC Mode Register91340.11.3 TSADCC Trigger Register91540.11.4 TSADCC Touch Screen Register91640.11.5 TSADCC Channel Enable Register91740.11.6 TSADCC Channel Disable Register91840.11.7 TSADCC Channel Status Register91940.11.8 TSADCC Status Register92040.11.9 TSADCC Channel Data Register x (x = 0..7)92240.11.10 TSADCC Last Converted Data Register92240.11.11 TSADCC Interrupt Enable Register92340.11.12 TSADCC Interrupt Disable Register92440.11.13 TSADCC Interrupt Mask Register92540.11.14 TSADCC X Position Data Register92640.11.15 TSADCC Z1 Data Register92640.11.16 TSADCC Z2 Data Register92740.11.17 TSADCC Manual Switch Command Register92740.11.18 TSADCC Write Protection Mode Register92840.11.19 TSADCC Write Protection Status Register92841. DMA Controller (DMAC)92941.1 Description92941.2 Embedded Characteristics92941.3 Block Diagram93141.4 Functional Description93241.4.1 Basic Definitions93241.4.2 Memory Peripherals93541.4.3 Handshaking Interface93541.4.3.1 Software Handshaking93541.4.3.2 Chunk Transactions93541.4.3.3 Single Transactions93541.4.4 DMAC Transfer Types93641.4.4.1 Multi-buffer Transfers93641.4.4.2 Buffer Chaining Using Linked Lists93641.4.4.3 Programming DMAC for Multiple Buffer Transfers93841.4.4.4 Replay Mode of Channel Registers93841.4.4.5 Contiguous Address Between Buffers93841.4.4.6 Suspension of Transfers Between buffers93941.4.4.7 Ending Multi-buffer Transfers93941.4.5 Programming a Channel94041.4.5.1 Programming Examples94041.4.5.2 Single-buffer Transfer (Row 1)94041.4.5.3 Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)94141.4.5.4 Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)94441.4.5.5 Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6)94741.4.5.6 Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)95041.4.5.7 Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)95341.4.6 Disabling a Channel Prior to Transfer Completion95741.4.6.1 Abnormal Transfer Termination95741.5 DMAC Software Requirements95841.6 DMA Controller (DMAC) User Interface95941.6.1 DMAC Global Configuration Register96041.6.2 DMAC Enable Register96141.6.3 DMAC Software Single Request Register96141.6.4 DMAC Software Chunk Transfer Request Register96241.6.5 DMAC Software Last Transfer Flag Register96341.6.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register96441.6.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register96541.6.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register96641.6.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register96741.6.10 DMAC Channel Handler Enable Register96841.6.11 DMAC Channel Handler Disable Register96941.6.12 DMAC Channel Handler Status Register97041.6.13 DMAC Channel x [x = 0..7] Source Address Register97141.6.14 DMAC Channel x [x = 0..7] Destination Address Register97141.6.15 DMAC Channel x [x = 0..7] Descriptor Address Register97241.6.16 DMAC Channel x [x = 0..7] Control A Register97341.6.17 DMAC Channel x [x = 0..7] Control B Register97541.6.18 DMAC Channel x [x = 0..7] Configuration Register97741.6.19 DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register97941.6.20 DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register98042. Pulse Width Modulation Controller (PWM)98142.1 Description98142.2 Embedded Characteristics98142.3 Block Diagram98242.4 I/O Lines Description98242.5 Product Dependencies98342.5.1 I/O Lines98342.5.2 Power Management98342.5.3 Interrupt Sources98342.6 Functional Description98342.6.1 PWM Clock Generator98442.6.2 PWM Channel98542.6.2.1 Block Diagram98542.6.2.2 Waveform Properties98542.6.3 PWM Controller Operations98842.6.3.1 Initialization98842.6.3.2 Source Clock Selection Criteria98842.6.3.3 Changing the Duty Cycle or the Period98842.6.3.4 Interrupts99042.7 Pulse Width Modulation Controller (PWM) User Interface99142.7.1 PWM Mode Register99242.7.2 PWM Enable Register99342.7.3 PWM Disable Register99342.7.4 PWM Status Register99442.7.5 PWM Interrupt Enable Register99442.7.6 PWM Interrupt Disable Register99542.7.7 PWM Interrupt Mask Register99542.7.8 PWM Interrupt Status Register99642.7.9 PWM Channel Mode Register99742.7.10 PWM Channel Duty Cycle Register99842.7.11 PWM Channel Period Register99942.7.12 PWM Channel Counter Register100042.7.13 PWM Channel Update Register100143. AC97 Controller (AC97C)100343.1 Description100343.2 Embedded Characteristics100343.3 Block Diagram100443.4 Pin Name List100543.5 Application Block Diagram100543.6 Product Dependencies100643.6.1 I/O Lines100643.6.2 Power Management100643.6.3 Interrupt100643.7 Functional Description100743.7.1 Protocol overview100743.7.2 Slot Description100843.7.2.1 Tag Slot100843.7.2.2 Codec Slot 1100843.7.2.3 Codec Slot 2100843.7.2.4 Data Slots [3:12]100843.7.3 AC97 Controller Channel Organization100943.7.3.1 AC97 Controller Setup101043.7.3.2 Transmit Operation101043.7.3.3 AC97 Output Frame101143.7.3.4 Receive Operation101143.7.3.5 AC97 Input Frame101243.7.3.6 Configuring and Using Interrupts101243.7.3.7 Endianness101243.7.3.8 To Transmit a Word Stored in Big Endian Format on AC-link101243.7.3.9 To Transmit A Halfword Stored in Big Indian Format on AC-link101243.7.3.10 To Transmit a10-bit Sample Stored in Big Endian Format on AC-link101343.7.3.11 To Receive Word transfers101343.7.3.12 To Receive Halfword Transfers101343.7.3.13 To Receive 10-bit Samples101343.7.4 Variable Sample Rate101443.7.5 Power Management101443.7.5.1 Powering Down the AC-Link101443.7.5.2 Waking up the AC-link101443.7.5.3 Wake-up Triggered by the AC97 Controller101443.7.5.4 Wake-up Triggered by the AC97 Codec101443.7.5.5 AC97 Codec Reset101543.7.5.6 Cold AC97 Reset101543.7.5.7 Warm AC97 Reset101543.8 AC97 Controller (AC97C) User Interface101643.8.1 AC97 Controller Mode Register101743.8.2 AC97 Controller Input Channel Assignment Register101843.8.3 AC97 Controller Output Channel Assignment Register101943.8.4 AC97 Controller Codec Channel Receive Holding Register102043.8.5 AC97 Controller Codec Channel Transmit Holding Register102143.8.6 AC97 Controller Channel A, Channel B, Receive Holding Register102243.8.7 AC97 Controller Channel A, Channel B, Transmit Holding Register102243.8.8 AC97 Controller Channel A Status Register102343.8.9 AC97 Controller Channel B Status Register102543.8.10 AC97 Controller Codec Status Register102743.8.11 AC97 Controller Channel A Mode Register102843.8.12 AC97 Controller Channel B Mode Register103043.8.13 AC97 Controller Codec Mode Register103243.8.14 AC97 Controller Status Register103343.8.15 AC97 Codec Controller Interrupt Enable Register103443.8.16 AC97 Controller Interrupt Disable Register103543.8.17 AC97 Controller Interrupt Mask Register103644. True Random Number Generator (TRNG)103744.1 Description103744.2 True Random Number Generator (TRNG) User Interface103844.2.1 TRNG Control Register103944.2.2 TRNG Interrupt Enable Register104044.2.3 TRNG Interrupt Disable Register104144.2.4 TRNG Interrupt Mask Register104244.2.5 TRNG Interrupt Status Register104344.2.6 TRNG Output Data Register104445. LCD Controller (LCDC)104545.1 Description104545.2 Embedded Characteristics104545.3 Block Diagram104645.4 I/O Lines Description104745.5 Product Dependencies104745.5.1 I/O Lines104745.5.2 Power Management104845.5.3 Interrupt Sources104845.6 Functional Description104945.6.1 DMA Controller104945.6.1.1 Configuration Block104945.6.1.2 AHB Interface104945.6.1.3 Channel-U104945.6.1.4 Channel-L105045.6.1.5 Control105045.6.2 LCD Controller Core105045.6.2.1 Configuration Block105045.6.2.2 Datapath105045.6.2.3 FIFO105145.6.2.4 Serializer105145.6.2.5 Palette105445.6.2.6 Dithering105445.6.2.7 Shifter105745.6.2.8 Timegen105745.6.2.9 Equation 1105945.6.2.10 Display106245.6.2.11 PWM106245.6.3 LCD Interface106245.7 Interrupts106845.8 Configuration Sequence106845.9 Double-buffer Technique106945.10 2D Memory Addressing107045.11 Register Configuration Guide107145.11.1 STN Mode Example107145.11.2 TFT Mode Example107145.12 LCD Controller (LCDC) User Interface107245.12.1 DMA Base Address Register 1107445.12.2 DMA Base Address Register 2107545.12.3 DMA Frame Pointer Register 1107645.12.4 DMA Frame Pointer Register 2107645.12.5 DMA Frame Address Register 1107745.12.6 DMA Frame Address Register 2107745.12.7 DMA Frame Configuration Register107845.12.8 DMA Control Register107945.12.9 LCD DMA 2D Addressing Register108045.12.10 LCD Control Register 1108145.12.11 LCD Control Register 2108245.12.12 LCD Timing Configuration Register 1108445.12.13 LCD Timing Configuration Register 2108545.12.14 LCD Frame Configuration Register108645.12.15 LCD FIFO Register108745.12.16 LCDMOD Toggle Rate Value Register108845.12.17 Dithering Pattern DP1_2 Register108945.12.18 Dithering Pattern DP4_7 Register108945.12.19 Dithering Pattern DP3_5 Register109045.12.20 Dithering Pattern DP2_3 Register109045.12.21 Dithering Pattern DP5_7 Register109145.12.22 Dithering Pattern DP3_4 Register109145.12.23 Dithering Pattern DP4_5 Register109245.12.24 Dithering Pattern DP6_7 Register109245.12.25 Power Control Register109345.12.26 Contrast Control Register109445.12.27 Contrast Value Register109545.12.28 LCD Interrupt Enable Register109645.12.29 LCD Interrupt Disable Register109745.12.30 LCD Interrupt Mask Register109845.12.31 LCD Interrupt Status Register109945.12.32 LCD Interrupt Clear Register110045.12.33 LCD Interrupt Test Register110145.12.34 LCD Interrupt Raw Status Register110245.12.35 LCD Write Protect Mode Register110345.12.36 LCD Write Protect Status Register110446. Video Decoder (VDEC)110546.1 Description110546.2 Embedded Characteristics110546.3 Block Diagram110646.3.1 Decoding Features110746.3.1.1 H.264 Features110746.3.1.2 MPEG-4 / H.263 Features110746.3.1.3 MPEG-2 Features110746.3.1.4 JPEG Features110846.3.1.5 VC-1 Features110846.3.1.6 Post Processing Features110946.3.2 Decoder Data Flow, Hardware Performs Entropy Decoding (VLC Mode)111046.3.3 Decoder Data Flow, Software Performs Entropy Decoding (RLC Mode)111146.4 Product Dependencies111346.4.1 Power Management111346.4.2 Interrupt111346.5 Video Decoder User Interface (VDEC) User Interface111446.6 Video Decoder Register Mapping (H.264)111646.6.1 Video Decoder ID Register111846.6.2 Decoder Interrupt Register111946.6.3 Decoder Device Configuration Register112146.6.4 Decoder Control Register 0 (Decoder Mode and Picture Type)112346.6.5 Decoder Control Register 1 (Picture Parameters)112546.6.6 Decoder Control Register 2 (H.264 Stream Decoding Table Selects)112646.6.7 Decoder Control Register 3 (Stream Buffer Information)112746.6.8 Decoder Control Register 4 (H.264 Control)112846.6.9 Decoder Control Register 5 (H.264 Control)112946.6.10 Decoder Control Register 6 (H.264 RLC Mode)113046.6.11 Decoder Control Register 6 (H.264 VLC Mode)113146.6.12 Differential Motion Vector Base Address (H.264, MPEG-4/H.263)113246.6.13 Decoder Control Register 7 (H264, MPEG-4/H.263)113346.6.14 RLC/VLC Data Base Address113446.6.15 Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture)113546.6.16 Reference Picture Index Base Address (H.264)113646.6.17 Reference Picture Number Register 0 (H.264)113746.6.18 Reference Picture Number Register 1 (H.264)113846.6.19 Reference Picture Number Register 2 (H.264)113946.6.20 Reference Picture Number Register 3 (H.264)114046.6.21 Reference Picture Number Register 4 (H.264)114146.6.22 Reference Picture Number Register 5 (H.264)114246.6.23 Reference Picture Number Register 6 (H.264)114346.6.24 Reference Picture Number Register 7 (H.264)114446.6.25 Reference Picture Long Term Flag Register (H.264)114546.6.26 Reference Picture Valid Flag Register (H.264)114646.6.27 Standard Dependent Tables Base Address114746.6.28 Direct Mode Motion Vector Base Address114846.6.29 H264 Initial Reference Picture List Register 0 (H.264)114946.6.30 H264 Initial Reference Picture List Register 1 (H.264)115046.6.31 H264 Initial Reference Picture List Register 2 (H.264)115146.6.32 H264 Initial Reference Picture List Register 3 (H.264)115246.6.33 H264 Initial Reference Picture List Register 4 (H.264)115346.6.34 H264 Initial Reference Picture List Register 5 (H.264)115446.6.35 Error Concealment Register115546.7 Video Decoder Register Mapping (MPEG-4/H.263)115646.7.1 Video Decoder ID Register115746.7.2 Decoder Interrupt Register115846.7.3 Decoder Device Configuration Register116046.7.4 Decoder Control Register 0 (Decoder Mode and Picture Type)116246.7.5 Decoder Control Register 1 (Picture Parameters)116446.7.6 Decoder Control Register 2 (MPEG-4/H.263 Stream Decoding Table Selects)116546.7.7 Decoder Control Register 3 (Stream Buffer Information)116646.7.8 Decoder Control Register 6 (MPEG-4/H.263 Base Address for MB-control)116746.7.9 Differential Motion Vector Base Address (H.264, MPEG-4/H.263)116846.7.10 Decoder Control Register 7 (H264, MPEG-4/H.263)116946.7.11 RLC/VLC Data Base Address117046.7.12 Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture)117146.7.13 Reference Picture Index 0 Base Address117246.7.14 Reference Picture Index 1 Base Address (Video)117346.7.15 Reference Picture Index 2 Base Address (Video)117446.7.16 Reference Picture Index 3 Base Address (Video)117546.7.17 Reference Picture Index 4 Base Address (MPEG-4/H.263 MVD Control)117646.7.18 Reference Picture Index 5 Base Address (MPEG-4/H.263 TRB/TRD Delta 0)117746.7.19 Reference Picture Index 6 Base Address (MPEG-4/H.263 TRB/TRD Delta -1)117846.7.20 Reference Picture Index 7 Base Address (MPEG-4/H.263 TRB/TRD Delta 1)117946.7.21 Standard Dependent Tables Base Address118046.7.22 Direct Mode Motion Vector Base Address118146.7.23 Error Concealment Register118246.8 Video Decoder Register Mapping (JPEG)118346.8.1 Video Decoder ID Register118446.8.2 Decoder Interrupt Register118546.8.3 Decoder Device Configuration Register118746.8.4 Decoder Control Register 0 (Decoder Mode and Picture Type)118946.8.5 Decoder Control Register 1 (Picture Parameters)119146.8.6 Decoder Control Register 2 (JPEG Stream Decoding Table Selects)119246.8.7 Decoder Control Register 3 (Stream Buffer Information)119446.8.8 RLC/VLC Data Base Address119546.8.9 Decoded Picture Base Address (JPEG Decoder Output Luma Picture)119646.8.10 Reference Picture Index 0 Base Address (JPEG Decoder Output Chroma Picture)119746.8.11 Reference Picture Index 1 Base Address (JPEG Control)119846.8.12 Reference Picture Index 2 Base Address (JPEG VLC Code Length First AC Table)119946.8.13 Reference Picture Index 3 Base Address (JPEG VLC Code length First AC Table)120046.8.14 Reference Picture Index 4 Base Address (JPEG VLC Code Length First ACTable)120146.8.15 Reference Picture Index 5 Base Address (JPEG VLC Code Length First/Second AC Table)120246.8.16 Reference Picture Index 6 Base Address (JPEG VLC Code Length Second AC Table)120346.8.17 Reference Picture Index 7 Base Address (JPEG VLC Code Length Second AC Table)120446.8.18 Reference Picture Index 8 Base Address (JPEG VLC Code Length Second AC Table)120546.8.19 Reference Picture Index 9 Base Address (JPEG VLC Code Length First DC Table)120646.8.20 Reference Picture Index 10 Base Address (JPEG VLC Code Length First DC Table)120746.8.21 Reference Picture Index 11 Base Address (JPEG VLC Code Length Second DC Table)120846.8.22 Reference Picture Index 12 Base Address (JPEG VLC Code Length Second DC Table)120946.8.23 Standard Dependent Tables Base Address121046.9 Video Decoder Register Mapping (VC-1)121146.9.1 Video Decoder ID Register121246.9.2 Decoder Interrupt Register121346.9.3 Decoder Device Configuration Register121546.9.4 Decoder Control Register 0 (Decoder Mode and Picture Type)121746.9.5 Decoder Control Register 1 (Picture Parameters)121946.9.6 Decoder Control Register 2 (VC-1 Stream Decoding Table Selects)122046.9.7 Decoder Control Register 3 (Stream Buffer Information)122246.9.8 Decoder Control Register 4 (VC-1 Control)122346.9.9 Decoder Control Register 5 (VC-1 Control)122546.9.10 Decoder Control Register 6 (VC-1 Intensity Control 0)122646.9.11 Differential Motion Vector Base Address (VC-1 Intensity Control 1)122746.9.12 Decoder Control Register 7 (VC-1 Intensity Control 2)122846.9.13 RLC/VLC Data Base Address122946.9.14 Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture)123046.9.15 Reference Picture Index 0 Base Address (Video, JPEG Decoder Output Chroma Picture)123146.9.16 Reference Picture Index 1 Base Address (Video)123246.9.17 Reference Picture Index 2 Base Address (Video)123346.9.18 Reference Picture Index 3 Base Address (Video)123446.9.19 Reference Picture Index 4 Base Address123546.9.20 Reference Picture Index 5 Base Address123746.9.21 Reference Picture Index 6 Base Address (VC-1 Intensity Control 4)123846.9.22 Reference Picture Index 13 Base Address (VC-1)123946.9.23 Direct Mode Motion Vector Base Address124046.9.24 Error Concealment Register124146.10 Video Decoder Register Mapping (MPEG-2/MPEG-1)124246.10.1 Video Decoder ID Register124346.10.2 Decoder Interrupt Register124446.10.3 Decoder Device Configuration Register124646.10.4 Decoder Control Register 0 (Decoder Mode And Picture Type)124846.10.5 Decoder Control Register 1 (Picture Parameters)125046.10.6 Decoder Control Register 2 (MPEG-2/MPEG-1 Stream Decoding Table Selects)125146.10.7 Decoder Control Register 3 (Stream Buffer Information)125246.10.8 RLC/VLC Data Base Address125346.10.9 Decoded Picture Base Address (Video)125446.10.10 Reference Picture Index 0 Base Address (Video)125546.10.11 Reference Picture Index 1 Base Address (Video)125646.10.12 Reference Picture Index 2 Base Address (Video)125746.10.13 Reference Picture Index 3 Base Address (Video)125846.10.14 Reference Picture Index 4 Base Address (MPEG-2/MPEG-1)125946.10.15 Standard Dependent Tables Base Address126046.10.16 Direct Mode Motion Vector Base Address126146.10.17 Error Concealment Register126246.11 Video Post-processor Register Mapping (All Decoders)126346.11.1 Post-Processor Interrupt Register126446.11.2 Post Processor Device Configuration Register126646.11.3 Post Processor Deinterlace Control Register126746.11.4 Post Processor Input Y Top Field Picture Base Address126846.11.5 Post Processor Input Cb Top Field Picture Base Address126946.11.6 Post Processor Input Cr Picture Base Address127046.11.7 Post Processor Output Y Picture Base Address127146.11.8 Post Processor Output C Picture Base Address127246.11.9 Post Processor Contrast Adjustment Register127346.11.10 Post Processor Contrast Adjustment and Color Conversion Register127446.11.11 Post Processor Color Conversion Register127546.11.12 Post Processor Color Conversion and Rotation Mode Register127646.11.13 Post Processor Input Picture Size and Cropping Register127746.11.14 Post Processor Input Y Bottom Field Picture Base Address127846.11.15 Post Processor Input Cb Bottom Field Picture Base Address127946.11.16 Post Processor R and G Padding and Scaling Ratio Register 0128046.11.17 Post Processor B Padding and Scaling Ratio Register 1128146.11.18 Post Processor Scaling Ratio Register 2128246.11.19 Post Processor Red Channel Mask Register128346.11.20 Post Processor Green Channel Mask Register128446.11.21 Post Processor Blue Channel Mask Register128546.11.22 Post Processor Control Register128646.11.23 Post Processor Mask 1 Start Coordinate Register128846.11.24 Post Processor Mask 2 Start Coordinate Register128946.11.25 Post Processor Mask 1 Size and PP Original Width Register129046.11.26 Post Processor Mask 2 Size Register129146.11.27 Post Processor Picture-in-Picture Register 0129246.11.28 Post Processor Dithering and Picture-in-Picture Register 1129346.11.29 Post Processor Display Width Register129446.11.30 Post Processor Alpha Blending GUI 1 Component Base Address129546.11.31 Post Processor Alpha Blending GUI 2 Component Base Address129647. SAM9M10 Electrical Characteristics129747.1 Absolute Maximum Ratings129747.2 DC Characteristics129747.3 Power Consumption129947.3.1 Power Consumption versus Modes129947.4 Clock Characteristics130147.4.1 Processor Clock Characteristics130147.4.2 Master Clock Characteristics130147.5 Main Oscillator Characteristics130147.5.1 Crystal Oscillator Characteristics130247.5.2 XIN Clock Characteristics130247.6 32 kHz Oscillator Characteristics130347.6.1 32 kHz Crystal Characteristics130347.6.2 XIN32 Clock Characteristics130447.7 32 kHz RC Oscillator Characteristics130447.8 PLL Characteristics130547.8.1 UTMI PLL Characteristics130547.9 I/Os130647.10 USB HS Characteristics130647.10.1 Electrical Characteristics130647.10.2 Static Power Consumption130647.10.3 Dynamic Power Consumption130747.11 Touch Screen ADC (TSADC)130847.12 Core Power Supply POR Characteristics130947.12.1 Power Sequence Requirements130947.12.2 Power-Up Sequence130947.13 SMC Timings131047.13.1 Timing Conditions131047.13.2 Timing Extraction131047.13.2.1 Zero Hold Mode Restrictions131047.13.2.2 Read Timings131047.13.2.3 Write Timings131147.14 DDRSDRC Timings131447.15 Peripheral Timings131447.15.1 SPI131447.15.1.1 Maximum SPI Frequency131447.15.1.2 Timing Conditions131447.15.1.3 Timing Extraction131547.15.2 SSC131847.15.2.1 Timing Conditions131847.15.2.2 Timing Extraction131947.15.3 ISI132247.15.3.1 Timing Conditions132247.15.3.2 Timing Extraction132347.15.4 HSMCI132347.15.5 EMAC132347.15.5.1 Timing Conditions132347.15.5.2 Timing Constraints132447.15.5.3 MII Mode132447.15.6 UART in SPI Mode132647.15.6.1 Timing Conditions132647.15.6.2 Timing Extraction132648. SAM9M10 Mechanical Characteristics132948.1 Package Drawings132948.2 Soldering Profile133049. SAM9M10 Ordering Information133250. SAM9M10 Errata133350.1 SAM9M10 Errata - Rev. A Parts133350.1.1 Boot ROM133350.1.1.1 Boot ROM: NAND Flash boot does not support ECC Correction133350.1.1.2 Boot ROM: Boot issue on AT45-series SPI dataflash133350.1.2 EMAC133350.1.2.1 EMAC: Setup Timing Violation in RMII Mode133350.1.3 Error Corrected Code Controller (ECC)133350.1.3.1 ECC: Computation with a 1 clock cycle long NRD/NWE pulse133350.1.3.2 Incomplete parity status when error in ECC parity133350.1.3.3 Unsupported ECC per 512 words133350.1.3.4 Unsupported hardware ECC on 16-bit Nand Flash133450.1.4 Pulse Width Modulation Controller (PWM)133450.1.4.1 PWM: Zero Period133450.1.5 RSTC: Software Reset During DDRAM Accesses133450.1.5.1 Software reset during DDRAM access133450.1.6 Static Memory Controller (SMC)133450.1.6.1 SMC Delay: Access133450.1.7 Serial Synchronous Controller (SSC)133450.1.7.1 SSC: Data sent without any frame synchro133450.1.7.2 SSC: Unexpected delay on TD output133550.1.8 Touch Screen (TSADCC)133550.1.8.1 TSADCC: Pen detect accuracy is not good133550.1.9 USB High Speed Host Port (UHPHS)133550.1.9.1 UHPHS: Packet Loss Issue in the UTMI Transceivers133550.1.10 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)133650.1.10.1 UHPHS/UDPHS: USB does not start after power-up133650.2 SAM9M10 Errata - Rev. B Parts133750.2.1 Boot ROM133750.2.1.1 Boot ROM: NAND Flash boot does not support ECC Correction133750.2.1.2 Boot ROM: Boot issue on AT45-series SPI dataflash133750.2.2 EMAC133750.2.2.1 EMAC: Setup Timing Violation in RMII Mode133750.2.3 Error Corrected Code Controller (ECC)133750.2.3.1 ECC: Computation with a 1 clock cycle long NRD/NWE pulse133750.2.3.2 Uncomplete parity status when error in ECC parity133750.2.3.3 Unsupported ECC per 512 words133750.2.3.4 Unsupported hardware ECC on 16-bit Nand Flash133850.2.4 Pulse Width Modulation Controller (PWM)133850.2.4.1 PWM: Zero Period133850.2.5 RSTC: Software Reset During DDRAM Accesses133850.2.5.1 Software reset during DDRAM access133850.2.6 Static Memory Controller (SMC)133850.2.6.1 SMC Delay: Access133850.2.7 Serial Synchronous Controller (SSC)133850.2.7.1 SSC: Data sent without any frame synchro133850.2.7.2 SSC: Unexpected delay on TD output133950.2.8 Touch Screen (TSADCC)133950.2.8.1 TSADCC: Pen detect accuracy is not good133950.2.9 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)133950.2.9.1 UHPHS/UDPHS: USB does not start after power-up133950.2.9.2 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL134050.3 SAM9M10 Errata - Rev. C Parts134150.3.1 Boot ROM134150.3.1.1 Boot ROM: NAND Flash boot does not support ECC Correction134150.3.2 EMAC134150.3.2.1 EMAC: Setup Timing Violation in RMII Mode134150.3.3 Error Corrected Code Controller (ECC)134150.3.3.1 ECC: Computation with a 1 clock cycle long NRD/NWE pulse134150.3.3.2 Uncomplete parity status when error in ECC parity134150.3.3.3 Unsupported ECC per 512 words134150.3.3.4 Unsupported hardware ECC on 16-bit Nand Flash134150.3.4 Pulse Width Modulation Controller (PWM)134250.3.4.1 PWM: Zero Period134250.3.5 RSTC: Software Reset During DDRAM Accesses134250.3.5.1 Software reset during DDRAM access134250.3.6 Static Memory Controller (SMC)134250.3.6.1 SMC Delay: Access134250.3.7 Serial Synchronous Controller (SSC)134250.3.7.1 SSC: Data sent without any frame synchro134250.3.7.2 SSC: Unexpected delay on TD output134250.3.8 Touch Screen (TSADCC)134350.3.8.1 TSADCC: Pen detect accuracy is not good134350.3.9 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)134350.3.9.1 UHPHS/UDPHS: USB does not start after power-up1343Revision History1345Table of Contents1349Size: 5.91 MBPages: 1361Language: EnglishOpen manual