Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Tightly-Coupled Memory Interface
5-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
5.1
About the tightly-coupled memory interface
The ARM926EJ-S processor enables low latency access to external memories using the
Tightly Coupled Memory (TCM) interface. The term tightly coupled memory refers to
the relationship between the ARM9EJ-S CPU core, and the operation of the memories,
where there is a strong correlation between the instruction and data access activity of
the ARM9EJ-S and the accesses made to external memory. This is in contrast to the
accesses made to the AHB interfaces, which are relatively decoupled from the
ARM9EJ-S core.
Tightly Coupled Memory (TCM) interface. The term tightly coupled memory refers to
the relationship between the ARM9EJ-S CPU core, and the operation of the memories,
where there is a strong correlation between the instruction and data access activity of
the ARM9EJ-S and the accesses made to external memory. This is in contrast to the
accesses made to the AHB interfaces, which are relatively decoupled from the
ARM9EJ-S core.
TCMs are intended for storing certain types of critical code or data, where low latency,
deterministic access is required. TCMs are not necessarily the best choice for all types
of such code or data, if code or data exhibit a high degree of spatial or temporal locality
better performance may be obtained by using cache memory. (See Chapter 4 Caches
and Write Buffer).
deterministic access is required. TCMs are not necessarily the best choice for all types
of such code or data, if code or data exhibit a high degree of spatial or temporal locality
better performance may be obtained by using cache memory. (See Chapter 4 Caches
and Write Buffer).
The ARM926EJ-S processor supports two TCM regions, one for instructions (ITCM)
and one for data (DTCM). The ITCM interface can also be accessed by the data side of
the ARM9EJ-S core. This is necessary for code to be loaded into the ITCM, for SWI
and emulated instruction handlers, and for accesses to PC-relative literal pools.
and one for data (DTCM). The ITCM interface can also be accessed by the data side of
the ARM9EJ-S core. This is necessary for code to be loaded into the ITCM, for SWI
and emulated instruction handlers, and for accesses to PC-relative literal pools.
The TCM address space is physically addressed, and the location of the TCM regions
in the physical address space is controlled by the TCM Region Register (see TCM
Region Register c9 on page 2-29). The physical size of the TCM regions are defined by
external inputs (IRSIZE, DRSIZE), and ranges from 4KB to 1MB. The encoding for
these pins is shown in TCM Size field encoding on page 2-30. The TCM regions can be
placed anywhere in the physical address map, with the restriction that the TCM base
address must be aligned with the TCM size, and that the instruction and data TCM
regions do not overlap. The TCM region size can be interrogated by software by reading
the TCM Status Register (see TCM Status Register c0 on page 2-12).
in the physical address space is controlled by the TCM Region Register (see TCM
Region Register c9 on page 2-29). The physical size of the TCM regions are defined by
external inputs (IRSIZE, DRSIZE), and ranges from 4KB to 1MB. The encoding for
these pins is shown in TCM Size field encoding on page 2-30. The TCM regions can be
placed anywhere in the physical address map, with the restriction that the TCM base
address must be aligned with the TCM size, and that the instruction and data TCM
regions do not overlap. The TCM region size can be interrogated by software by reading
the TCM Status Register (see TCM Status Register c0 on page 2-12).
The INITRAM pin allows the ARM926EJ-S processor to boot from instruction TCM
space after system reset. If INITRAM is asserted during system reset and the VINITHI
pin is deasserted, then the ARM926EJ-S processor fetches the instruction at
space after system reset. If INITRAM is asserted during system reset and the VINITHI
pin is deasserted, then the ARM926EJ-S processor fetches the instruction at
0x00000000
from the instruction TCM interface. (If both INITRAM and VINITHI are asserted, the
first instruction fetch after reset is from
first instruction fetch after reset is from
0xFFFF0000
over the AHB).
The TCM interface supports memory accesses with zero or more wait-states. The
requirement to support zero wait state accesses imposes various constraints on the TCM
sub-system design that do not apply when interfacing memories with a generic bus
interface such as AHB.
requirement to support zero wait state accesses imposes various constraints on the TCM
sub-system design that do not apply when interfacing memories with a generic bus
interface such as AHB.
Because of timing restrictions, read accesses occur on the TCM interface without prior
qualification by the MMU. This means that all reads on the TCM interface must be
treated as being speculative, and consequently precludes the use of read-sensitive
qualification by the MMU. This means that all reads on the TCM interface must be
treated as being speculative, and consequently precludes the use of read-sensitive