Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Noncachable Instruction Fetches
7-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
7.1
About noncachable instruction fetches
The ARM926EJ-S processor performs speculative noncachable instruction fetches to
increase performance. Speculative instruction fetching is enabled at reset. This can be
disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register
c15 on page 2-36). If prefetching is disabled only instruction fetches issued directly by
the ARM9EJ-S core result in instruction fetches on the AHB interface.
increase performance. Speculative instruction fetching is enabled at reset. This can be
disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register
c15 on page 2-36). If prefetching is disabled only instruction fetches issued directly by
the ARM9EJ-S core result in instruction fetches on the AHB interface.
The following subsection is divided into:
•
•
•
7.1.1
Uses of noncachable code
Although noncachable code performance has been improved compared with other
ARM9 family cached cores, it is still recommended that the ICache is used in
preference, where practical.
ARM9 family cached cores, it is still recommended that the ICache is used in
preference, where practical.
Noncachable code has previously been used for boot loaders of operating systems and
for preventing cache pollution. It is worth noting that the ICache can be enabled without
the MMU being enabled (see Chapter 4 Caches and Write Buffer), and that cache
pollution can be controlled using the cache lockdown register (see Cache Lockdown and
TCM Region Registers c9 on page 2-26).
for preventing cache pollution. It is worth noting that the ICache can be enabled without
the MMU being enabled (see Chapter 4 Caches and Write Buffer), and that cache
pollution can be controlled using the cache lockdown register (see Cache Lockdown and
TCM Region Registers c9 on page 2-26).
7.1.2
Self modifying code
A four-word buffer is used to hold speculatively fetched instructions. Only sequential
instructions are fetched speculatively, and in the event of the ARM9EJ-S core issuing a
nonsequential instruction fetch, the contents of the buffer are discarded (flushed). In
situations where the contents of the prefetch buffer might become invalid during a
sequence of sequential instruction fetches by the ARM9EJ-S core (for example, turning
the MMU on or off, or turning on the ICache), the prefetch buffer is also flushed. This
avoids the requirement for an explicit Instruction Memory Barrier (IMB) operation to
be performed, except when self-modifying code is used. Because the prefetch buffer is
flushed when the ARM9EJ-S core issues a nonsequential instruction fetch, a branch
instruction (or equivalent) can be used to implement the required IMB behavior. This is
illustrated by the following code sequence:
instructions are fetched speculatively, and in the event of the ARM9EJ-S core issuing a
nonsequential instruction fetch, the contents of the buffer are discarded (flushed). In
situations where the contents of the prefetch buffer might become invalid during a
sequence of sequential instruction fetches by the ARM9EJ-S core (for example, turning
the MMU on or off, or turning on the ICache), the prefetch buffer is also flushed. This
avoids the requirement for an explicit Instruction Memory Barrier (IMB) operation to
be performed, except when self-modifying code is used. Because the prefetch buffer is
flushed when the ARM9EJ-S core issues a nonsequential instruction fetch, a branch
instruction (or equivalent) can be used to implement the required IMB behavior. This is
illustrated by the following code sequence:
LDMIA
R0,{R1-R5} ; load code sequence into R1-R5
ADR
R0,self_mod_code
STMIA
R0,{R1-R5} ; store code sequence (nonbuffered region)
B
self_mod_code
; branch to modified code
self_mod_code: