Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Signal Descriptions
A-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
A.1
Signal properties and requirements
To ensure ease of integration of the ARM926EJ-S processor into embedded
applications, and to simplify synthesis flow, the following design techniques have been
used:
applications, and to simplify synthesis flow, the following design techniques have been
used:
•
a single rising edge clock times all activity
•
all signals and buses are unidirectional
•
all inputs are required to be synchronous to the single clock.
These techniques simplify the definition of the top-level ARM926EJ-S processor
signals because all outputs change from the rising edge and all inputs are sampled with
the rising edge of the clock. In addition, all signals are either input or output only.
Bidirectional signals are not used.
signals because all outputs change from the rising edge and all inputs are sampled with
the rising edge of the clock. In addition, all signals are either input or output only.
Bidirectional signals are not used.
Note
You must use external logic to synchronize asynchronous signals (for example interrupt
sources) before applying them to the ARM926EJ-S processor.
sources) before applying them to the ARM926EJ-S processor.