Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

A-7

Table A-3 describes the ARM926EJ-S processor debug signals.

Communications 
channel receive

Output

When HIGH, this signal denotes that the comms 
channel receive buffer contains valid data waiting to 
be read.

Communications 
channel transmit

Output

When HIGH, this signal denotes that the comms 
channel transmit buffer is empty.

Debug acknowledge

Output

When HIGH indicates that the processor is in debug 
state.

Data watchpoint

Input

Asserted by external hardware to halt execution of 
the processor for debug purposes. If HIGH at the end 
of a data memory request cycle, it causes the 
ARM926EJ-S processor to enter debug state.

Debug enable

Input

Enables the debug features of the processor. This 
signal must be tied LOW if debug is not required.

EmbeddedICE-RT 
external input

Input

Inputs to the EmbeddedICE-RT logic that enable 
breakpoints or watchpoints to be dependent on 
external conditions.

Instruction breakpoint

Input

Asserted by external hardware to halt execution of 
the processor for debug purposes. If HIGH at the end 
of an instruction fetch, it causes the ARM926EJ-S 
processor to enter debug state if that instruction 
reaches the Execute stage of the processor pipeline.

Instruction executed

Output

Indicates that the instruction in the Execute stage of 
the processor pipeline has been executed.