Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

B-5

You can access the Trace Control Register by using the following instructions:

MCR p15, 1, <Rd>, c15, c1, 0

; Write Trace Control Register

MRC p15, 1, <Rd>, c15, c1, 0

; Read Trace Control Register

You can use the Trace Control Register to determine under what conditions the 
ARM9EJ-S core is stalled when the FIFOFULL signal is asserted. 

Usually, non-invasive real-time trace requires the presence of an nFIQ or nIRQ 
interrupt to prevent the ARM9EJ-S core being stalled by FIFOFULL being asserted. 

The Trace Control Register enables you to modify this behavior, so that the presence of 
an interrupt does not prevent the ARM9EJ-S core being stalled if FIFOFULL is 
asserted.

Table B-2 shows the bit assignments for the Trace Control Register. Bits [2:1] of this 
register are reset to 0. 

The MMU test operations support accessing TLB structures in the MMU and are used 
in conjunction with the Debug and Test Address Register. 

You can access the MMU test operations using the instructions in Table B-3.

[31:3]

Reserved (Should Be Zero)

[2]

1 = FIQ interrupt does not prevent FIFOFULL from stalling the ARM9EJ-S core 
0 = FIQ interrupt prevents FIFOFULL from stalling the ARM9EJ-S core

[1]

1 = IRQ interrupt does not prevent FIFOFULL from stalling the ARM9EJ-S core 
0 = IRQ interrupt prevents FIFOFULL from stalling the ARM9EJ-S core

[0]

Reserved (Should Be Zero)

MRC p15, 4/5, <Rd>, c15, c2, 0
MCR p15, 4/5, <Rd>, c15, c3, 0

Read tag in main TLB entry
Write tag in main TLB entry