Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
CP15 Test and Debug Registers
B-12
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
The data to be written or read is placed in ARM register Rd with the format shown in
Figure B-4 on page B-8.
Figure B-4 on page B-8.
B.1.5
Cache Debug Control Register
The Cache Debug Control Register is used to force specific cache behavior required for
debug.
debug.
The following instructions can be used to access the Cache Debug Control Register:
MRC{cond} p15,7,<Rd>,c15,c0,0 ; read cache debug control register
MCR{cond} p15,7,<Rd>,c15,c0,0 ; write cache debug control register
MCR{cond} p15,7,<Rd>,c15,c0,0 ; write cache debug control register
The Cache Debug Control Register format is shown in Figure B-7.
Figure B-7 Cache Debug Control Register format
The Cache Debug Control Register bit assignments are listed in Table B-9. The reset
value of the Cache Debug Control Register is
value of the Cache Debug Control Register is
0x0
.
0
SBZ
DDL
1
2
DIL
DWB
31
3
Table B-9 Cache Debug Control Register bit assignments
Bit
Name
Function Description
[31:3]
-
Reserved
Read = Unpredictable
Write = Should Be Zero
Write = Should Be Zero
[2]
DWB
Disable write-back (force WT)
0 = Enable write-back behavior
1 = Force write-through behavior
1 = Force write-through behavior
[1]
DIL
Disable ICache linefill
0 = Enable ICache linefills
1 = Disable ICache linefills
1 = Disable ICache linefills
[0]
DDL
Disable DCache linefill
0 = Enable DCache linefills
1 = Disable DCache linefills
1 = Disable DCache linefills