Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Introduction
1-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
1.1
About the ARM926EJ-S processor
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose
microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all
important.
microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all
important.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction
sets, enabling the user to trade off between high performance and high code density. The
ARM926EJ-S processor includes features for efficient execution of Java byte codes,
providing Java performance similar to JIT, but without the associated code overhead.
sets, enabling the user to trade off between high performance and high code density. The
ARM926EJ-S processor includes features for efficient execution of Java byte codes,
providing Java performance similar to JIT, but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic
to assist in both hardware and software debug. The ARM926EJ-S processor has a
Harvard cached architecture and provides a complete high-performance processor
subsystem, including:
to assist in both hardware and software debug. The ARM926EJ-S processor has a
Harvard cached architecture and provides a complete high-performance processor
subsystem, including:
•
an ARM9EJ-S integer core
•
a Memory Management Unit (MMU)
•
separate instruction and data AMBA AHB bus interfaces
•
separate instruction and data TCM interfaces.
The ARM926EJ-S processor provides support for external coprocessors enabling
floating-point or other application-specific hardware acceleration to be added. The
ARM926EJ-S processor implements ARM architecture version 5TEJ.
floating-point or other application-specific hardware acceleration to be added. The
ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM926EJ-S processor is a synthesizable macrocell. This means that you can
optimize the macrocell for a particular target library, and that you can configure the
memory system to suit your target application. You can individually configure the cache
sizes to be any power of two between 4KB and 128KB.
optimize the macrocell for a particular target library, and that you can configure the
memory system to suit your target application. You can individually configure the cache
sizes to be any power of two between 4KB and 128KB.
The tightly-coupled instruction and data memories are instantiated externally to the
ARM926EJ-S macrocell, providing you with the flexibility of optimizing the memory
subsystem for performance, power, and particular RAM type. The TCM interfaces
enable nonzero wait state memory to be attached, as well as providing a mechanism for
supporting DMA.
ARM926EJ-S macrocell, providing you with the flexibility of optimizing the memory
subsystem for performance, power, and particular RAM type. The TCM interfaces
enable nonzero wait state memory to be attached, as well as providing a mechanism for
supporting DMA.
Figure 1-1 on page 1-3 shows the main blocks in the ARM926EJ-S processor.