Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

Glossary-19

The memory system indicates to the processor that a write has been completed at a point 
in the transaction where the memory system is able to guarantee that the effect of the 
write is visible to all processors in the system. This is not the case if the write is 
associated with a memory synchronization primitive, or is to a Device or Strongly 
Ordered region. In these cases the memory system might only indicate completion of 
the write when the access has affected the state of the target, unless it is impossible to 
distinguish between having the effect of the write visible and having the state of target 
updated. 

This stricter requirement for some types of memory ensures that any side-effects of the 
memory access can be guaranteed by the processor to have taken place. You can use this 
to prevent the starting of a subsequent operation in the program order until the 
side-effects are visible.

In a write-through cache, data is written to main memory at the same time as the cache 
is updated. 

See Write-through.