Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-7
2.3
Register descriptions
The following registers are described in this section:
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2.3.1
ID Code, Cache Type, and TCM Status Registers, c0
Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
Reading from this register returns the device ID, the cache type, or the TCM status
depending on the value of Opcode_2 used:
Reading from this register returns the device ID, the cache type, or the TCM status
depending on the value of Opcode_2 used:
Opcode_2 = 0 ID value.
Opcode_2 = 1 instruction and data cache type.
Opcode_2 = 2 TCM status.
The CRm field Should Be Zero when reading from these registers. Table 2-4 shows the
instructions you can use to read register c0.
instructions you can use to read register c0.
Writing to register c0 is Unpredictable.
Table 2-4 Reading from register c0
Function
Instruction
Read ID code
MRC p15,0,<Rd>,c0,c0,{0, 3-7}
Read cache type
MRC p15,0,<Rd>,c0,c0,1
Read TCM status
MRC p15,0,<Rd>,c0,c0,2