Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Programmer’s Model
2-22
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Table 2-18 lists the cache operation functions and the associated data and instruction
formats for c7.
formats for c7.
Prefetch ICache line
Performs an ICache lookup of the specified modified
virtual address. If the cache misses, and the region is
cachable, a linefill is performed.
virtual address. If the cache misses, and the region is
cachable, a linefill is performed.
Drain write buffer
This instruction acts as an explicit memory barrier. It drains
the contents of the write buffers of all memory stores
occurring in program order before this instruction is
completed. No instructions occurring in program order
after this instruction are executed until it completes. This
can be used when timing of specific stores to the level two
memory system has to be controlled (for example, when a
store to an interrupt acknowledge location has to complete
before interrupts are enabled).
the contents of the write buffers of all memory stores
occurring in program order before this instruction is
completed. No instructions occurring in program order
after this instruction are executed until it completes. This
can be used when timing of specific stores to the level two
memory system has to be controlled (for example, when a
store to an interrupt acknowledge location has to complete
before interrupts are enabled).
Wait for interrupt
This instruction drains the contents of the write buffers,
puts the processor into a low-power state, and stops it from
executing further instructions until an interrupt (or debug
request) occurs. When an interrupt does occur, the MCR
instruction completes and the IRQ or FIQ handler is entered
as normal. The return link in R14_irq or R14_fiq contains
the address of the MCR instruction plus eight, so that the
typical instruction used for interrupt return (
puts the processor into a low-power state, and stops it from
executing further instructions until an interrupt (or debug
request) occurs. When an interrupt does occur, the MCR
instruction completes and the IRQ or FIQ handler is entered
as normal. The return link in R14_irq or R14_fiq contains
the address of the MCR instruction plus eight, so that the
typical instruction used for interrupt return (
SUBS
PC,R14,#4
) returns to the instruction following the MCR.
Table 2-17 Function descriptions register c7 (continued)
Function
Description
Table 2-18 Cache operations c7
Function/operation
Data format
Instruction
Invalidate ICache and DCache
SBZ
MCR p15, 0, <Rd>, c7, c7, 0
Invalidate ICache
SBZ
MCR p15, 0, <Rd>, c7, c5, 0
Invalidate ICache single entry (MVA)
MVA
MCR p15, 0, <Rd>, c7, c5, 1
Invalidate ICache single entry (Set/Way)
Set/Way
MCR p15, 0, <Rd>, c7, c5, 2
Prefetch ICache line (MVA)
MVA
MCR p15, 0, <Rd>, c7, c13, 1
Invalidate DCache
SBZ
MCR p15, 0, <Rd>, c7, c6, 0
Invalidate DCache single entry (MVA)
MVA
MCR p15, 0, <Rd>, c7, c6, 1