Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

2-31

If either the data or instruction TCM is disabled, then the contents of the respective 
TCM are not accessed. If the TCM is subsequently re-enabled, the contents will not 
have been changed by the ARM926EJ-S processor.

For a Harvard arrangement, the instruction-side TCM must be accessible for both reads 
and writes during normal operation, and for loading code, or for debug activity. This 
enables accesses to literal pools, undefined instruction emulation, and parameter 
passing for SWI operations. You must insert an Instruction Memory Barrier (IMB) 
between a write to the instruction TCM and the instructions being read from the 
instruction TCM. See Chapter 9 Instruction Memory Barrier for more details.

 Instruction fetches from the data TCM are not possible. An attempt to fetch an 
instruction from an address in the data TCM space does not result in an access to the 
data TCM, and the instruction is fetched from main memory. These accesses can result 
in external aborts, because the address range might not be supported in main memory.

The instruction TCM must not be programmed to the same base address as the data 
TCM. If the two TCMs are of different sizes, the regions in physical memory must not 
overlap. If they do overlap, it is Unpredictable which memory is accessed.

 The base address value setting must be aligned to the TCM size.

64KB

b0111

128KB

b1000

256KB

b1001

512KB

b1010

1MB

b1011

Reserved

b1100, b1101, 
b1110, b1111