Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Memory Management Unit
3-6
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
3.2.1
Translation table base
The hardware translation process is initiated when the TLB does not contain a
translation for the requested MVA. The Translation Table Base Register (TTBR), CP15
register c2, points to the base address of a table in physical memory that contains section
or page descriptors, or both. The 14 low-order bits [13:0] of the TTBR are
Unpredictable on a read, and the table must reside on a 16KB boundary. Figure 3-1
shows the format of the TTBR.
translation for the requested MVA. The Translation Table Base Register (TTBR), CP15
register c2, points to the base address of a table in physical memory that contains section
or page descriptors, or both. The 14 low-order bits [13:0] of the TTBR are
Unpredictable on a read, and the table must reside on a 16KB boundary. Figure 3-1
shows the format of the TTBR.
Figure 3-1 Translation Table Base Register
The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual
memory. This enables up to 4GB of virtual memory to be addressed.
memory. This enables up to 4GB of virtual memory to be addressed.
Figure 3-2 on page 3-7 shows the table walk process.
Translation table base
31
14 13
0