Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Memory Management Unit
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
3-11
Section descriptor bit assignments are described in Table 3-4.
3.2.5
Coarse page table descriptor
A coarse page table descriptor provides the base address of a page table that contains
second-level descriptors for either large page or small page accesses. Coarse page tables
have 256 entries, splitting the 1MB that the table describes into 4KB blocks. Figure 3-6
shows the format of a coarse page table descriptor.
second-level descriptors for either large page or small page accesses. Coarse page tables
have 256 entries, splitting the 1MB that the table describes into 4KB blocks. Figure 3-6
shows the format of a coarse page table descriptor.
Figure 3-6 Coarse page table descriptor
Note
If a coarse page table descriptor is returned from the first-level fetch, a second-level
fetch is initiated.
fetch is initiated.
Table 3-4 Section descriptor bits
Bits
Description
[31:20]
Form the corresponding bits of the physical address for a section
[19:12]
Always written as 0
[11:10]
The AP bits specify the access permissions for this section
[9]
Always written as 0
[8:5]
Specify one of the 16 possible domains (held in the domain access control register)
that contain the primary access controls
that contain the primary access controls
[4]
Should be written as 1, for backwards compatibility
[3:2]
These bits (C and B) indicate if the area of memory mapped by this section is
treated as write-back cachable, write-through cachable, noncached buffered, or
noncached nonbuffered
treated as write-back cachable, write-through cachable, noncached buffered, or
noncached nonbuffered
[1:0]
These bits must be 10 to indicate a section descriptor
1
Coarse page table base address
31
10 9 8
5 4 3 2 1 0
S
B
Z
Domain
1 SBZ 0