Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Memory Management Unit
3-16
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
The two least significant bits of the second-level descriptor indicate the descriptor type
as shown in Table 3-8.
as shown in Table 3-8.
Note
Tiny pages do not support subpage permissions and therefore only have one set of
access permission bits.
access permission bits.
3.2.9
Translating large page references
Figure 3-10 on page 3-17 shows the complete translation sequence for a 64KB large
page.
page.
[11:4]
[11:4]
[5:4]
Access permission bits. Domain access control on page 3-24
and Fault checking sequence on page 3-26 show how to
interpret the access permission bits.
and Fault checking sequence on page 3-26 show how to
interpret the access permission bits.
[3:2]
[3:2]
[3:2]
These bits, C and B, indicate whether the area of memory
mapped by this page is treated as write-back cachable,
write-through cachable, noncached buffered, or noncached
nonbuffered.
mapped by this page is treated as write-back cachable,
write-through cachable, noncached buffered, or noncached
nonbuffered.
[1:0]
[1:0]
[1:0]
These bits indicate the page size and validity and are
interpreted as shown in Table 3-8.
interpreted as shown in Table 3-8.
Table 3-8 Interpreting page table entry bits [1:0]
Value
Meaning
Description
0 0
Invalid
Generates a page translation fault
0 1
Large page
Indicates that this is a 64KB page
1 0
Small page
Indicates that this is a 4KB page
1 1
Tiny page
Indicates that this is a 1KB page
Table 3-7 Second-level descriptor bits (continued)
Bits
Description
Large
Small
Tiny