Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Memory Management Unit
3-24
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
3.4
Domain access control
MMU accesses are primarily controlled through the use of domains. There are 16
domains and each has a two-bit field to define access to it. Two types of user are
supported:
domains and each has a two-bit field to define access to it. Two types of user are
supported:
•
clients
•
managers.
The domains are defined in the domain access control register, CP15 c3. Figure 2-7 on
page 2-18 shows how the 32 bits of the register are allocated to define the 16 two-bit
domains.
page 2-18 shows how the 32 bits of the register are allocated to define the 16 two-bit
domains.
Table 3-11 defines how the bits within each domain are interpreted to specify the access
permissions.
permissions.
Table 3-12 shows how to interpret the Access Permission (AP) bits and how their
interpretation is dependent on the R and S bits (Control Register c1 bits [9:8]).
interpretation is dependent on the R and S bits (Control Register c1 bits [9:8]).
Table 3-11 Domain access control register, access control bits
Value
Meaning
Description
0 0
No access
Any access generates a domain fault.
0 1
Client
Accesses are checked against the access permission bits in
the section or page descriptor.
the section or page descriptor.
1 0
Reserved
Reserved. Currently behaves like the no access mode.
1 1
Manager
Accesses are not checked against the access permission
bits so a permission fault cannot be generated.
bits so a permission fault cannot be generated.
Table 3-12 Interpreting access permission (AP) bits
AP
S
R
Privileged permissions
User permissions
0 0
0
0
No access
No access
0 0
1
0
Read-only
No access
0 0
0
1
Read-only
Read-only
0 0
1
1
Unpredictable
Unpredictable