Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Memory Management Unit
3-30
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Note
Because the same register, CP15 c1, controls the enabling of the ICache, DCache, and
the MMU, all three can be enabled using a single MCR instruction.
the MMU, all three can be enabled using a single MCR instruction.
3.6.2
Disabling the MMU
To disable the MMU, clear bit 0 in CP15 c1.
Note
If the MMU is enabled, then disabled, and subsequently re-enabled, the contents of the
TLB are preserved. If these are now invalid, then the TLB must be invalidated before
re-enabling the MMU. See TLB Operations Register c8 on page 2-24.
TLB are preserved. If these are now invalid, then the TLB must be invalidated before
re-enabling the MMU. See TLB Operations Register c8 on page 2-24.