Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

123

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

RSTC_SR

0xFFFFFE04

Read-only

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.

1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.  

Registers the NRST Pin Level at Master Clock (MCK).

0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 

1 = A software reset command is being performed by the reset controller. The reset controller is busy.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

SRCMP

NRSTL

15

14

13

12

11

10

9

8

–

–

–

–

–

RSTTYP

7

6

5

4

3

2

1

0

–

–

–

–

–

–

–

URSTS

0

0

0

General Reset

Both VDDCORE and VDDBU rising

0

0

1

Wake Up Reset

VDDCORE rising

0

1

0

Watchdog Reset

Watchdog fault occurred

0

1

1

Software Reset

Processor reset required by the software

1

0

0

User Reset

NRST pin detected low