Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

327

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

When an MLC write page operation is performed, the PMECC controller is configured with the
NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system
information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of
the PMECCFG register is set to one. When the NAND spare area contains only redundancy
information, the SPAREEN bit is set to zero.

When the write page operation is terminated, the user writes the redundancy in the NAND spare
area. This operation can be done with DMA assistance.

0

PMECC_ECC0

PMECC_ECC0

1

PMECC_ECC0, PMECC_ECC1

PMECC_ECC0, PMECC_ECC1

2

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3

3

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3, 
PMECC_ECC4, PMECC_ECC5, 
PMECC_ECC6

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3, 
PMECC_ECC4, PMECC_ECC5, 
PMECC_ECC6

4

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3, 
PMECC_ECC4, PMECC_ECC5, 
PMECC_ECC6, PMECC_ECC7, 
PMECC_ECC8, PMECC_ECC9

PMECC_ECC0, PMECC_ECC1, 
PMECC_ECC2, PMECC_ECC3, 
PMECC_ECC4, PMECC_ECC5, 
PMECC_ECC6, PMECC_ECC7, 
PMECC_ECC8, PMECC_ECC9, 
PMECC_ECC10

0

4 bytes

4 bytes

1

7 bytes

7 bytes

2

13 bytes

14 bytes

3

20 bytes

21 bytes

4

39 bytes

42 bytes