Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
376
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Figure 29-12.Write Cycle
29.9.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the
address bus to the point where address may change. The total write cycle time is equal to:
address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the
hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the
hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
29.9.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of
consecutive write cycles in the same memory (see
consecutive write cycles in the same memory (see
). However, for devices that perform write operations on
the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS2, NBS3,
A0, A1
NCS
NWE_SETUP
NWE_PULSE
NWE_HOLD
MCK
NWE
NCS_WR_SETUP
NCS_WR_PULSE
NCS_WR_HOLD
NWE_CYCLE