Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during

the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.

To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).

If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.

The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR).

List of the write-protected registers:

z

z

z

z

z

All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to
their type. 

The SMC_SETUP register groups the definition of all setup parameters:

• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP

The SMC_PULSE register groups the definition of all pulse parameters:

• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE

The SMC_CYCLE register groups the definition of all cycle parameters:

• NRD_CYCLE, NWE_CYCLE

MCK

D[31:0]

NCS

NWE, 

NWR0, NWR1, 
NWR2, NWR3  

A

[25:2]

NBS0, NBS1,
NBS2, NBS3,
A0, A1