Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
771
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
39.
Universal Synchronous Asynchronous Receiver Transmitter (USART)
39.1
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications
with slow remote devices. Multidrop communications are also supported through address bit handling in reception and
transmission.
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications
with slow remote devices. Multidrop communications are also supported through address bit handling in reception and
transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485, LIN, and SPI buses, with ISO7816 T = 0
or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow
control by automatic management of the pins RTS and CTS.
or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow
control by automatic management of the pins RTS and CTS.
The USART supports the connection to the DMA Controller, which enables data transfers to the transmitter and from
the receiver. The DMAC provides chained buffer management without any intervention of the processor.
the receiver. The DMAC provides chained buffer management without any intervention of the processor.