Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
772
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
39.2
Embedded Characteristics
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Programmable Baud Rate Generator
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5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
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1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
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Parity Generation and Error Detection
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Framing Error Detection, Overrun Error Detection
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MSB-first or LSB-first
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Optional Break Generation and Detection
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By-8 or by-16 Over-sampling Receiver Frequency
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Optional Hardware Handshaking RTS-CTS
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Receiver Time-out and Transmitter Timeguard
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Optional Multidrop Mode with Address Generation and Detection
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RS485 with Driver Control Signal
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ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
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NACK Handling, Error Counter with Repetition and Iteration Limit
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IrDA Modulation and Demodulation
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Communication at up to 115.2 Kbps
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SPI Mode
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Master or Slave
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Serial Clock Programmable Phase and Polarity
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SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
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LIN Mode
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Compliant with LIN 1.3 and LIN 2.0 specifications
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Master or Slave
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Processing of frames with up to 256 data bytes
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Response Data length can be configurable or defined automatically by the Identifier
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Self synchronization in Slave node configuration
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Automatic processing and verification of the “Synch Break” and the “Synch Field”
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The “Synch Break” is detected even if it is partially superimposed with a data byte
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Automatic Identifier parity calculation/sending and verification
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Parity sending and verification can be disabled
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Automatic Checksum calculation/sending and verification
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Checksum sending and verification can be disabled
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Support both “Classic” and “Enhanced” checksum types
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Full LIN error checking and reporting
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Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
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Generation of the Wakeup signal
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Test Modes
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Remote Loopback, Local Loopback, Automatic Echo
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Supports Connection of:
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Two DMA Controller Channels (DMAC)
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Offers Buffer Transfer without Processor Intervention