Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
106
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
named EXTERNAL_RESET_LENGTH, lasts 2
(ERSTL+1)
Slow Clock cycles. This gives the approximate duration of an
assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven
low for a time compliant with potential external devices connected on the system reset.
low for a time compliant with potential external devices connected on the system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for
devices requiring a longer startup time than the Slow Clock Oscillator.
devices requiring a longer startup time than the Slow Clock Oscillator.
14.4.3 BMS Sampling
The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is
sampled three slow clock cycles after the Core Power-On-Reset output rising edge.
sampled three slow clock cycles after the Core Power-On-Reset output rising edge.
Figure 14-3. BMS Sampling
14.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset
status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the
processor reset is released.
status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the
processor reset is released.
14.4.4.1 General Reset
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is
filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock
oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock
Oscillator startup time.
filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock
oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock
Oscillator startup time.
After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper
processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General
Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General
Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the
Main Supply POR Cell does not report a Main Supply shutdown.
Main Supply POR Cell does not report a Main Supply shutdown.
VDDBU only activates the backup_nreset signal.
The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR
output).
output).
SLCK
Core Supply
POR output
BMS sampling delay
= 3 cycles
BMS Signal
proc_nreset
XXX
H or L