Data Sheet (AT91SAM9X35-EK)Table of ContentsSection 15Introduction51.1 Scope51.2 Applicable Documents6Section 27Kit Contents72.1 Deliverables72.2 Evaluation Board Specifications82.3 Electrostatic Warning9Section 310Power Up103.1 Power Up the Board103.2 DevStart103.3 Recovery Procedure113.4 Sample Code and Technical Support11Section 412Evaluation Kit Hardware124.1 Introduction124.2 Computer Module (CM)144.2.1 CM Board Overview144.2.2 Equipment List144.2.3 Function Blocks164.2.4 Configuration254.2.5 Connectors264.2.6 Schematics274.3 EK Board Description324.3.1 EK Board Overview324.3.2 Equipment List334.3.3 Function Blocks344.3.4 Configuration504.3.5 Connectors564.3.6 Schematics744.4 Optional Display Module (DM) Board Hardware894.4.1 DM Board Overview894.4.2 Equipment List894.4.3 Function Blocks894.4.4 Schematics93Section 594Revision History945.1 Revision History94Size: 6.38 MBPages: 95Language: EnglishOpen manual
Data Sheet (AT91SAM9X35-EK)Table of ContentsDescription11. Features22. Block Diagram43. Signal Description54. Package and Pinout94.1 Overview of the 217-ball BGA Package94.2 I/O Description94.2.1 Reset State104.3 217-ball BGA Package Pinout115. Power Considerations175.1 Power Supplies176. Memories186.1 Memory Mapping196.2 Embedded Memories196.2.1 Internal SRAM196.2.2 Internal ROM196.3 External Memories196.3.1 External Bus Interface196.3.2 Static Memory Controller196.3.3 DDR2SDR Controller207. System Controller217.1 Chip Identification237.2 Backup Section238. Peripherals248.1 Peripheral Mapping248.2 Peripheral Identifiers248.3 Peripheral Signal Multiplexing on I/O Lines259. ARM926EJ-S™269.1 Description269.2 Embedded Characteristics279.3 Block Diagram289.4 ARM9EJ-S Processor299.4.1 ARM9EJ-S Operating States299.4.2 Switching State299.4.3 Instruction Pipelines299.4.4 Memory Access299.4.5 Jazelle Technology299.4.6 ARM9EJ-S Operating Modes309.4.7 ARM9EJ-S Registers309.4.7.1 Status Registers319.4.7.2 Exceptions329.4.8 ARM Instruction Set Overview339.4.9 New ARM Instruction Set349.4.10 Thumb Instruction Set Overview359.5 CP15 Coprocessor369.5.1 CP15 Registers Access379.6 Memory Management Unit (MMU)389.6.1 Access Control Logic389.6.2 Translation Look-aside Buffer (TLB)389.6.3 Translation Table Walk Hardware399.6.4 MMU Faults399.7 Caches and Write Buffer399.7.1 Instruction Cache (ICache)399.7.2 Data Cache (DCache) and Write Buffer409.7.2.1 DCache409.7.2.2 Write Buffer409.8 Bus Interface Unit419.8.1 Supported Transfers419.8.2 Thumb Instruction Fetches419.8.3 Address Alignment4110. Debug and Test4210.1 Description4210.2 Embedded Characteristics4210.3 Block Diagram4310.4 Application Examples4410.4.1 Debug Environment4410.4.2 Test Environment4510.5 Debug and Test Pin Description4610.6 Functional Description4710.6.1 Test Pin4710.6.2 EmbeddedICE™4710.6.3 JTAG Signal Description4710.6.4 Debug Unit4710.6.5 IEEE 1149.1 JTAG Boundary Scan4810.6.6 JTAG ID Code Register4911. Boot Strategies5011.1 ROM Code5011.2 Flow Diagram5011.3 Chip Setup5111.4 NVM Boot5111.4.1 NVM Boot Sequence5111.4.2 NVM Bootloader Program Description5311.4.3 Valid Code Detection5411.4.3.1 ARM Exception Vectors Check5411.4.3.2 boot.bin File Check5511.4.4 Detailed Memory Boot Procedures5511.4.4.1 NAND Flash Boot: NAND Flash Detection5511.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction5811.4.4.3 SD Card Boot6011.4.4.4 SPI Flash Boot6011.4.4.5 TWI EEPROM Boot6011.4.5 Hardware and Software Constraints6011.5 SAM-BA Monitor6211.5.1 Command List6211.5.2 DBGU Serial Port6311.5.2.1 Supported External Crystal/External Clocks6311.5.2.2 Xmodem Protocol6311.5.3 USB Device Port6411.5.3.1 Supported External Crystal / External Clocks6411.5.3.2 USB Class6411.5.3.3 Enumeration Process6411.5.3.4 Communication Endpoints6512. Boot Sequence Controller (BSC)6612.1 Description6612.2 Embedded Characteristics6612.3 Product Dependencies6612.4 Boot Sequence Controller (BSC) User Interface6712.4.1 Boot Sequence Configuration Register6813. Advanced Interrupt Controller (AIC)6913.1 Description6913.2 Embedded Characteristics6913.3 Block Diagram7013.4 Application Block Diagram7013.5 AIC Detailed Block Diagram7013.6 I/O Line Description7113.7 Product Dependencies7113.7.1 I/O Lines7113.7.2 Power Management7113.7.3 Interrupt Sources7113.8 Functional Description7213.8.1 Interrupt Source Control7213.8.1.1 Interrupt Source Mode7213.8.1.2 Interrupt Source Enabling7213.8.1.3 Interrupt Clearing and Setting7213.8.1.4 Interrupt Status7213.8.2 Interrupt Latencies7413.8.3 Normal Interrupt7513.8.3.1 Priority Controller7513.8.3.2 Interrupt Nesting7513.8.3.3 Interrupt Vectoring7613.8.3.4 Interrupt Handlers7613.8.4 Fast Interrupt7713.8.4.1 Fast Interrupt Source7713.8.4.2 Fast Interrupt Control7713.8.4.3 Fast Interrupt Vectoring7713.8.4.4 Fast Interrupt Handlers7813.8.4.5 Fast Forcing7813.8.5 Protect Mode7913.8.6 Spurious Interrupt8013.8.7 General Interrupt Mask8013.9 Write Protection Registers8113.10 Advanced Interrupt Controller (AIC) User Interface8213.10.1 Base Address8213.10.2 AIC Source Mode Register8313.10.3 AIC Source Vector Register8413.10.4 AIC Interrupt Vector Register8513.10.5 AIC FIQ Vector Register8613.10.6 AIC Interrupt Status Register8713.10.7 AIC Interrupt Pending Register8813.10.8 AIC Interrupt Mask Register8913.10.9 AIC Core Interrupt Status Register9013.10.10 AIC Interrupt Enable Command Register9113.10.11 AIC Interrupt Disable Command Register9213.10.12 AIC Interrupt Clear Command Register9313.10.13 AIC Interrupt Set Command Register9413.10.14 AIC End of Interrupt Command Register9513.10.15 AIC Spurious Interrupt Vector Register9613.10.16 AIC Debug Control Register9713.10.17 AIC Fast Forcing Enable Register9813.10.18 AIC Fast Forcing Disable Register9913.10.19 AIC Fast Forcing Status Register10013.10.20 AIC Write Protect Mode Register10113.10.21 AIC Write Protect Status Register10214. Reset Controller (RSTC)10314.1 Description10314.2 Embedded Characteristics10314.3 Block Diagram10414.4 Functional Description10514.4.1 Reset Controller Overview10514.4.2 NRST Manager10514.4.2.1 NRST Signal10514.4.2.2 NRST External Reset Control10514.4.3 BMS Sampling10614.4.4 Reset States10614.4.4.1 General Reset10614.4.4.2 Wake-up Reset10714.4.4.3 User Reset10814.4.4.4 Software Reset10914.4.4.5 Watchdog Reset11014.4.5 Reset State Priorities11114.4.6 Reset Controller Status Register11214.5 Reset Controller (RSTC) User Interface11314.5.1 Reset Controller Control Register11414.5.2 Reset Controller Status Register11514.5.3 Reset Controller Mode Register11615. Real-time Clock (RTC)11715.1 Description11715.2 Embedded Characteristics11715.3 Block Diagram11815.4 Product Dependencies11915.4.1 Power Management11915.4.2 Interrupt11915.5 Functional Description11915.5.1 Reference Clock11915.5.2 Timing11915.5.3 Alarm11915.5.4 Error Checking when Programming12015.5.5 Updating Time/Calendar12015.6 Real-time Clock (RTC) User Interface12215.6.1 RTC Control Register12315.6.2 RTC Mode Register12415.6.3 RTC Time Register12515.6.4 RTC Calendar Register12615.6.5 RTC Time Alarm Register12715.6.6 RTC Calendar Alarm Register12815.6.7 RTC Status Register12915.6.8 RTC Status Clear Command Register13015.6.9 RTC Interrupt Enable Register13115.6.10 RTC Interrupt Disable Register13215.6.11 RTC Interrupt Mask Register13315.6.12 RTC Valid Entry Register13416. Periodic Interval Timer (PIT)13516.1 Description13516.2 Embedded Characteristics13516.3 Block Diagram13616.4 Functional Description13716.5 Periodic Interval Timer (PIT) User Interface13816.5.1 Periodic Interval Timer Mode Register13916.5.2 Periodic Interval Timer Status Register14016.5.3 Periodic Interval Timer Value Register14116.5.4 Periodic Interval Timer Image Register14217. Watchdog Timer (WDT)14317.1 Description14317.2 Embedded Characteristics14317.3 Block Diagram14417.4 Functional Description14517.5 Watchdog Timer (WDT) User Interface14717.5.1 Watchdog Timer Control Register14817.5.2 Watchdog Timer Mode Register14917.5.3 Watchdog Timer Status Register15018. Shutdown Controller (SHDWC)15118.1 Description15118.2 Embedded Characteristics15118.3 Block Diagram15218.4 I/O Lines Description15318.5 Product Dependencies15318.5.1 Power Management15318.6 Functional Description15418.7 Shutdown Controller (SHDWC) User Interface15518.7.1 Shutdown Control Register15618.7.2 Shutdown Mode Register15718.7.3 Shutdown Status Register15819. General Purpose Backup Registers (GPBR)15919.1 Description15919.2 Embedded Characteristics15919.3 General Purpose Backup Registers (GPBR) User Interface16019.3.1 General Purpose Backup Register x16020. Slow Clock Controller (SCKC)16120.1 Description16120.2 Embedded Characteristics16120.3 Block Diagram16220.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator16320.3.2 Bypass the 32768 Hz Oscillator16320.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator16320.4 Slow Clock Configuration (SCKC) User Interface16420.4.1 Slow Clock Configuration Register16421. Clock Generator (CKGR)16521.1 Description16521.2 Embedded Characteristics16521.3 CKGR Block Diagram16621.4 Slow Clock Selection16721.4.1 Switch from Internal 32 kHz RC Oscillator to the 32768 Hz Crystal16721.4.2 Bypass the 32768 Hz Oscillator16721.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator16821.4.4 Slow Clock Configuration Register16921.5 Main Clock17021.6 Main Clock Selection17121.6.1 Fast wake-up17121.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal17221.6.3 Bypass the 12 MHz Oscillator17221.6.4 Switch from the 12 MHz Crystal to Internal 12 MHz RC Oscillator17221.6.5 12 MHz Fast RC Oscillator17221.6.6 12 to 16 MHz Crystal Oscillator17221.6.7 Main Clock Oscillator Selection17321.6.8 Main Clock Frequency Counter17321.7 Divider and PLLA Block17321.7.1 Divider and Phase Lock Loop Programming17421.8 UTMI Phase Lock Loop Programming17422. Power Management Controller (PMC)17522.1 Description17522.2 Embedded Characteristics17522.3 Master Clock Controller17622.4 Block Diagram17722.5 Processor Clock Controller17822.6 USB Device and Host Clocks17822.7 LP-DDR/DDR2 Clock17822.8 Software Modem Clock17822.9 Peripheral Clock Controller17822.10 Programmable Clock Output Controller17922.11 Programming Sequence17922.12 Clock Switching Details18222.12.1 Master Clock Switching Timings18222.12.2 Clock Switching Waveforms18322.13 Power Management Controller (PMC) User Interface18522.13.1 PMC System Clock Enable Register18622.13.2 PMC System Clock Disable Register18722.13.3 PMC System Clock Status Register18822.13.4 PMC Peripheral Clock Enable Register18922.13.5 PMC Peripheral Clock Disable Register19022.13.6 PMC Peripheral Clock Status Register19122.13.7 PMC UTMI Clock Configuration Register19222.13.8 PMC Clock Generator Main Oscillator Register19322.13.9 PMC Clock Generator Main Clock Frequency Register19422.13.10 PMC Clock Generator PLLA Register19522.13.11 PMC Master Clock Register19622.13.12 PMC USB Clock Register19722.13.13 PMC SMD Clock Register19822.13.14 PMC Programmable Clock Register19922.13.15 PMC Interrupt Enable Register20022.13.16 PMC Interrupt Disable Register20122.13.17 PMC Status Register20222.13.18 PMC Interrupt Mask Register20422.13.19 PLL Charge Pump Current Register20522.13.20 PMC Write Protect Mode Register20622.13.21 PMC Write Protect Status Register20722.13.22 PMC Peripheral Control Register20823. Parallel Input/Output (PIO) Controller20923.1 Description20923.2 Embedded Characteristics20923.3 Block Diagram21023.4 Product Dependencies21123.4.1 Pin Multiplexing21123.4.2 External Interrupt Lines21123.4.3 Power Management21123.4.4 Interrupt Generation21123.5 Functional Description21223.5.1 Pull-up and Pull-down Resistor Control21323.5.2 I/O Line or Peripheral Function Selection21323.5.3 Peripheral A or B or C or D Selection21323.5.4 Output Control21423.5.5 Synchronous Data Output21423.5.6 Multi Drive Control (Open Drain)21423.5.7 Output Line Timings21423.5.8 Inputs21523.5.9 Input Glitch and Debouncing Filters21523.5.10 Input Edge/Level Interrupt21623.5.10.1 Example21723.5.10.2 Interrupt Mode Configuration21823.5.10.3 Edge or Level Detection Configuration21823.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.21823.5.11 I/O Lines Lock21823.5.12 Programmable I/O Delays21823.5.13 Programmable I/O Drive21923.5.14 Programmable Schmitt Trigger21923.5.15 Write Protection Registers21923.6 I/O Lines Programming Example22123.7 Parallel Input/Output Controller (PIO) User Interface22223.7.1 PIO Enable Register22523.7.2 PIO Disable Register22523.7.3 PIO Status Register22623.7.4 PIO Output Enable Register22623.7.5 PIO Output Disable Register22723.7.6 PIO Output Status Register22723.7.7 PIO Input Filter Enable Register22823.7.8 PIO Input Filter Disable Register22823.7.9 PIO Input Filter Status Register22923.7.10 PIO Set Output Data Register22923.7.11 PIO Clear Output Data Register23023.7.12 PIO Output Data Status Register23023.7.13 PIO Pin Data Status Register23123.7.14 PIO Interrupt Enable Register23123.7.15 PIO Interrupt Disable Register23223.7.16 PIO Interrupt Mask Register23223.7.17 PIO Interrupt Status Register23323.7.18 PIO Multi-driver Enable Register23323.7.19 PIO Multi-driver Disable Register23423.7.20 PIO Multi-driver Status Register23423.7.21 PIO Pull Up Disable Register23523.7.22 PIO Pull Up Enable Register23523.7.23 PIO Pull Up Status Register23623.7.24 PIO Peripheral ABCD Select Register 123723.7.25 PIO Peripheral ABCD Select Register 223823.7.26 PIO Input Filter Slow Clock Disable Register23923.7.27 PIO Input Filter Slow Clock Enable Register23923.7.28 PIO Input Filter Slow Clock Status Register24023.7.29 PIO Slow Clock Divider Debouncing Register24023.7.30 PIO Pad Pull Down Disable Register24123.7.31 PIO Pad Pull Down Enable Register24123.7.32 PIO Pad Pull Down Status Register24223.7.33 PIO Output Write Enable Register24323.7.34 PIO Output Write Disable Register24323.7.35 PIO Output Write Status Register24423.7.36 PIO Additional Interrupt Modes Enable Register24423.7.37 PIO Additional Interrupt Modes Disable Register24523.7.38 PIO Additional Interrupt Modes Mask Register24523.7.39 PIO Edge Select Register24623.7.40 PIO Level Select Register24623.7.41 PIO Edge/Level Status Register24723.7.42 PIO Falling Edge/Low Level Select Register24723.7.43 PIO Rising Edge/High Level Select Register24823.7.44 PIO Fall/Rise - Low/High Status Register24823.7.45 PIO Lock Status Register24923.7.46 PIO Write Protect Mode Register25023.7.47 PIO Write Protect Status Register25123.7.48 PIO Schmitt Trigger Register25223.7.49 PIO I/O Delay Register25223.7.50 PIO I/O Drive Register 125323.7.51 PIO I/O Drive Register 225424. Debug Unit (DBGU)25524.1 Description25524.2 Embedded Characteristics25524.3 Block Diagram25624.4 Product Dependencies25724.4.1 I/O Lines25724.4.2 Power Management25724.4.3 Interrupt Source25724.5 UART Operations25724.5.1 Baud Rate Generator25724.5.2 Receiver25824.5.2.1 Receiver Reset, Enable and Disable25824.5.2.2 Start Detection and Data Sampling25824.5.2.3 Receiver Ready25924.5.2.4 Receiver Overrun25924.5.2.5 Parity Error25924.5.2.6 Receiver Framing Error26024.5.3 Transmitter26024.5.3.1 Transmitter Reset, Enable and Disable26024.5.3.2 Transmit Format26024.5.3.3 Transmitter Control26024.5.4 DMA Support26124.5.5 Test Modes26124.5.6 Debug Communication Channel Support26224.5.7 Chip Identifier26324.5.8 ICE Access Prevention26324.6 Debug Unit (DBGU) User Interface26424.6.1 Debug Unit Control Register26524.6.2 Debug Unit Mode Register26624.6.3 Debug Unit Interrupt Enable Register26724.6.4 Debug Unit Interrupt Disable Register26824.6.5 Debug Unit Interrupt Mask Register26924.6.6 Debug Unit Status Register27024.6.7 Debug Unit Receiver Holding Register27124.6.8 Debug Unit Transmit Holding Register27124.6.9 Debug Unit Baud Rate Generator Register27224.6.10 Debug Unit Chip ID Register27324.6.11 Debug Unit Chip ID Extension Register27724.6.12 Debug Unit Force NTRST Register27825. Bus Matrix (MATRIX)27925.1 Description27925.2 Embedded Characteristics27925.2.1 Matrix Masters28025.2.2 Matrix Slaves28025.2.3 Master to Slave Access28125.3 Memory Mapping28125.4 Special Bus Granting Mechanism28125.4.1 No Default Master28225.4.2 Last Access Master28225.4.3 Fixed Default Master28225.5 Arbitration28225.5.1 Arbitration Scheduling28325.5.1.1 Undefined Length Burst Arbitration28325.5.1.2 Slot Cycle Limit Arbitration28325.5.2 Arbitration Priority Scheme28425.5.2.1 Fixed Priority Arbitration28425.5.2.2 Round-Robin Arbitration28425.6 Register Write Protection28525.7 Bus Matrix (MATRIX) User Interface28625.7.1 Bus Matrix Master Configuration Registers28825.7.2 Bus Matrix Slave Configuration Registers28925.7.3 Bus Matrix Priority Registers A For Slaves29025.7.4 Bus Matrix Priority Registers B For Slaves29125.7.5 Bus Matrix Master Remap Control Register29225.7.6 EBI Chip Select Assignment Register29325.7.7 Write Protection Mode Register29525.7.8 Write Protection Status Register29626. External Bus Interface (EBI)29726.1 Description29726.2 Embedded Characteristics29726.3 EBI Block Diagram29826.4 I/O Lines Description29926.5 Application Example30026.5.1 Hardware Interface30026.5.2 Product Dependencies30226.5.2.1 I/O Lines30226.5.3 Functional Description30226.5.3.1 Bus Multiplexing30226.5.3.2 Pull-up and Pull-down Control30226.5.3.3 Drive Level and Delay Control30326.5.3.4 Power supplies30426.5.3.5 Static Memory Controller30526.5.3.6 DDR2SDRAM Controller30526.5.3.7 Programmable Multibit ECC Controller30626.5.3.8 NAND Flash Support30626.5.4 Implementation Examples30726.5.4.1 2x8-bit DDR2 on EBI30726.5.4.2 16-bit LPDDR on EBI30826.5.4.3 16-bit SDRAM on EBI30926.5.4.4 2x16-bit SDRAM on EBI31026.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 031126.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 031226.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 131326.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 131426.5.4.9 NOR Flash on NCS031527. Programmable Multibit ECC Controller (PMECC)31627.1 Description31627.2 Embedded Characteristics31627.3 Block Diagram31727.4 Functional Description31827.4.1 MLC/SLC Write Page Operation using PMECC32027.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set32127.4.1.2 MLC/SLC Write Operation with Spare Area Disabled32127.4.2 MLC/SLC Read Page Operation using PMECC32227.4.2.1 MLC/SLC Read Operation with Spare Decoding32227.4.2.2 MLC/SLC Read Operation32227.4.2.3 MLC/SLC User Read ECC Area32327.5 Software Implementation32327.5.1 Remainder Substitution Procedure32327.5.2 Find the Error Location Polynomial Sigma(x)32427.5.3 Find the Error Position32627.6 Programmable Multibit ECC Controller (PMECC) User Interface32827.6.1 PMECC Configuration Register33027.6.2 PMECC Spare Area Size Register33227.6.3 PMECC Start Address Register33327.6.4 PMECC End Address Register33427.6.5 PMECC Clock Control Register33527.6.6 PMECC Control Register33627.6.7 PMECC Status Register33727.6.8 PMECC Interrupt Enable Register33827.6.9 PMECC Interrupt Disable Register33927.6.10 PMECC Interrupt Mask Register34027.6.11 PMECC Interrupt Status Register34127.6.12 PMECC ECC x Register34227.6.13 PMECC Remainder x Register34328. Programmable Multibit ECC Error Location Controller (PMERRLOC)34428.1 Description34428.2 Embedded Characteristics34428.3 Block Diagram34428.4 Functional Description34528.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface34628.5.1 Error Location Configuration Register34728.5.2 Error Location Primitive Register34828.5.3 Error Location Enable Register34928.5.4 Error Location Disable Register35028.5.5 Error Location Status Register35128.5.6 Error Location Interrupt Enable Register35228.5.7 Error Location Interrupt Disable Register35328.5.8 Error Location Interrupt Mask Register35428.5.9 Error Location Interrupt Status Register35528.5.10 Error Location SIGMAx Register35628.5.11 PMECC Error Locationx Register35729. Static Memory Controller (SMC)35829.1 Description35829.2 Embedded Characteristics35829.3 I/O Lines Description35929.4 Multiplexed Signals35929.5 Application Example36029.5.1 Hardware Interface36029.6 Product Dependencies36029.6.1 I/O Lines36029.7 External Memory Mapping36129.8 Connection to External Devices36129.8.1 Data Bus Width36129.8.2 Byte Write or Byte Select Access36129.8.2.1 Byte Write Access36329.8.2.2 Byte Select Access36329.8.2.3 Signal Multiplexing36429.9 Standard Read and Write Protocols36529.9.1 Read Waveforms36529.9.1.1 NRD Waveform36529.9.1.2 NCS Waveform36529.9.1.3 Read Cycle36629.9.1.4 Null Delay Setup and Hold36629.9.1.5 Null Pulse36729.9.2 Read Mode36729.9.2.1 Read is Controlled by NRD (READ_MODE = 1):36729.9.2.2 Read is Controlled by NCS (READ_MODE = 0)36729.9.3 Write Waveforms36829.9.3.1 NWE Waveforms36829.9.3.2 NCS Waveforms36829.9.3.3 Write Cycle36929.9.3.4 Null Delay Setup and Hold36929.9.3.5 Null Pulse37029.9.4 Write Mode37029.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)37029.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)37129.9.5 Write Protected Registers37229.9.6 Coding Timing Parameters37229.9.7 Reset Values of Timing Parameters37229.9.8 Usage Restriction37229.10 Automatic Wait States37329.10.1 Chip Select Wait States37329.10.2 Early Read Wait State37429.10.3 Reload User Configuration Wait State37629.10.3.1 User Procedure37629.10.3.2 Slow Clock Mode Transition37629.10.4 Read to Write Wait State37629.11 Data Float Wait States37729.11.1 READ_MODE37729.11.2 TDF Optimization Enabled (TDF_MODE = 1)37829.11.3 TDF Optimization Disabled (TDF_MODE = 0)37929.12 External Wait38129.12.1 Restriction38129.12.2 Frozen Mode38229.12.3 Ready Mode38429.12.4 NWAIT Latency and Read/Write Timings38629.13 Slow Clock Mode38729.13.1 Slow Clock Mode Waveforms38729.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode38829.14 Asynchronous Page Mode38929.14.1 Protocol and Timings in Page Mode39029.14.2 Byte Access Type in Page Mode39129.14.3 Page Mode Restriction39129.14.4 Sequential and Non-sequential Accesses39129.15 Programmable IO Delays39229.16 Static Memory Controller (SMC) User Interface39329.16.1 SMC Setup Register39429.16.2 SMC Pulse Register39529.16.3 SMC Cycle Register39629.16.4 SMC MODE Register39729.16.5 SMC DELAY I/O Register39929.16.6 SMC Write Protect Mode Register40029.16.7 SMC Write Protect Status Register40130. DDR SDR SDRAM Controller (DDRSDRC)40230.1 Description40230.2 Embedded Characteristics40330.3 DDRSDRC Module Diagram40430.4 Initialization Sequence40530.4.1 SDR-SDRAM Initialization40530.4.2 Low-power DDR1-SDRAM Initialization40530.4.3 DDR2-SDRAM Initialization40630.5 Functional Description40830.5.1 SDRAM Controller Write Cycle40830.5.2 SDRAM Controller Read Cycle41330.5.3 Refresh (Auto-refresh Command)41730.5.4 Power Management41730.5.4.1 Self Refresh Mode41730.5.4.2 Power-down Mode42030.5.4.3 Deep Power-down Mode42130.5.4.4 Reset Mode42230.5.5 Multi-port Functionality42230.5.6 Write Protected Registers42430.6 Software Interface/SDRAM Organization, Address Mapping42530.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks42530.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks42730.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width42730.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface42930.7.1 DDRSDRC Mode Register43030.7.2 DDRSDRC Refresh Timer Register43130.7.3 DDRSDRC Configuration Register43230.7.4 DDRSDRC Timing Parameter 0 Register43530.7.5 DDRSDRC Timing Parameter 1 Register43730.7.6 DDRSDRC Timing Parameter 2 Register43830.7.7 DDRSDRC Low-power Register43930.7.8 DDRSDRC Memory Device Register44130.7.9 DDRSDRC DLL Register44230.7.10 DDRSDRC High Speed Register44330.7.11 DDRSDRC Write Protect Mode Register44430.7.12 DDRSDRC Write Protect Status Register44531. DMA Controller (DMAC)44631.1 Description44631.2 Embedded Characteristics44631.2.1 DMA Controller 044731.2.2 DMA Controller 144831.3 Block Diagram44931.4 Functional Description45031.4.1 Basic Definitions45031.4.2 Memory Peripherals45231.4.3 Handshaking Interface45331.4.3.1 Software Handshaking45331.4.4 DMAC Transfer Types45331.4.4.1 Multi-buffer Transfers45431.4.4.2 Programming DMAC for Multiple Buffer Transfers45531.4.4.3 Ending Multi-buffer Transfers45631.4.5 Programming a Channel45631.4.5.1 Programming Examples45631.4.6 Disabling a Channel Prior to Transfer Completion47331.4.6.1 Abnormal Transfer Termination47331.5 DMAC Software Requirements47431.6 Write Protection Registers47531.7 DMA Controller (DMAC) User Interface47631.7.1 DMAC Global Configuration Register47731.7.2 DMAC Enable Register47831.7.3 DMAC Software Single Request Register47931.7.4 DMAC Software Chunk Transfer Request Register48031.7.5 DMAC Software Last Transfer Flag Register48131.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register48231.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register48331.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register48431.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register48531.7.10 DMAC Channel Handler Enable Register48631.7.11 DMAC Channel Handler Disable Register48731.7.12 DMAC Channel Handler Status Register48831.7.13 DMAC Channel x [x = 0..7] Source Address Register48931.7.14 DMAC Channel x [x = 0..7] Destination Address Register49031.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register49131.7.16 DMAC Channel x [x = 0..7] Control A Register49231.7.17 DMAC Channel x [x = 0..7] Control B Register49431.7.18 DMAC Channel x [x = 0..7] Configuration Register49631.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register49831.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register49931.7.21 DMAC Write Protect Mode Register50031.7.22 DMAC Write Protect Status Register50132. USB High Speed Device Port (UDPHS)50232.1 Description50232.2 Embedded Characteristics50232.3 Block Diagram50332.4 Typical Connection50432.5 Product Dependencies50432.5.1 Power Management50432.5.2 Interrupt50432.6 Functional Description50532.6.1 UTMI Transceivers Sharing50532.6.2 USB V2.0 High Speed Device Port Introduction50532.6.3 USB V2.0 High Speed Transfer Types50532.6.4 USB Transfer Event Definitions50632.6.5 USB V2.0 High Speed BUS Transactions50632.6.6 Endpoint Configuration50732.6.7 DPRAM Management50932.6.8 Transfer With DMA51032.6.9 Transfer Without DMA51132.6.10 Handling Transactions with USB V2.0 Device Peripheral51232.6.10.1 Setup Transaction51232.6.10.2 NYET51232.6.10.3 Data IN51232.6.10.4 Bulk IN or Interrupt IN51232.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)51332.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)51332.6.10.7 Isochronous IN51732.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example51732.6.10.9 Data OUT51832.6.10.10 Bulk OUT or Interrupt OUT51832.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)51832.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)51832.6.10.13 High Bandwidth Isochronous Endpoint OUT52032.6.10.14 Isochronous Endpoint Handling: OUT Example52032.6.10.15 STALL52132.6.11 Speed Identification52132.6.12 USB V2.0 High Speed Global Interrupt52132.6.13 Endpoint Interrupts52232.6.14 Power Modes52432.6.14.1 Controlling Device States52432.6.14.2 Not Powered State52432.6.14.3 Entering Attached State52532.6.14.4 From Powered State to Default State (Reset)52532.6.14.5 From Default State to Address State (Address Assigned)52532.6.14.6 From Address State to Configured State (Device Configured)52532.6.14.7 Entering Suspend State (Bus Activity)52532.6.14.8 Receiving a Host Resume52532.6.14.9 Sending an External Resume52632.6.15 Test Mode52632.7 USB High Speed Device Port (UDPHS) User Interface52732.7.1 UDPHS Control Register52832.7.2 UDPHS Frame Number Register53032.7.3 UDPHS Interrupt Enable Register53132.7.4 UDPHS Interrupt Status Register53232.7.5 UDPHS Clear Interrupt Register53432.7.6 UDPHS Endpoints Reset Register53532.7.7 UDPHS Test Register53632.7.8 UDPHS Endpoint Configuration Register53832.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)54032.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)54232.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)54432.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)54632.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)54832.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)55132.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)55432.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)55532.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)55632.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)55732.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)55832.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)56132.7.21 UDPHS DMA Channel Transfer Descriptor56432.7.22 UDPHS DMA Next Descriptor Address Register56432.7.23 UDPHS DMA Channel Address Register56532.7.24 UDPHS DMA Channel Control Register56632.7.25 UDPHS DMA Channel Status Register56833. USB Host High Speed Port (UHPHS)57033.1 Description57033.2 Embedded Characteristics57033.3 Block Diagram57133.4 Typical Connection57233.5 Product Dependencies57333.5.1 I/O Lines57333.5.2 Power Management57333.5.3 Interrupt57433.6 Functional Description57533.6.1 UTMI transceivers Sharing57533.6.2 EHCI57533.6.3 OHCI57534. High Speed MultiMedia Card Interface (HSMCI)57634.1 Description57634.2 Embedded Characteristics57634.3 Block Diagram57734.4 Application Block Diagram57734.5 Pin Name List57834.6 Product Dependencies57834.6.1 I/O Lines57834.6.2 Power Management57834.6.3 Interrupt57834.7 Bus Topology57934.8 High Speed MultiMedia Card Operations58134.8.1 Command - Response Operation58134.8.2 Data Transfer Operation58434.8.3 Read Operation58434.8.4 Write Operation58634.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller58834.8.6 READ_SINGLE_BLOCK Operation using DMA Controller58934.8.6.1 Block Length is Multiple of 458934.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)59034.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)59234.8.7 WRITE_MULTIPLE_BLOCK59334.8.7.1 One Block per Descriptor59334.8.8 READ_MULTIPLE_BLOCK59434.8.8.1 Block Length is a Multiple of 459434.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)59534.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)59734.9 SD/SDIO Card Operation59834.9.1 SDIO Data Transfer Type59834.9.2 SDIO Interrupts59834.10 CE-ATA Operation59834.10.1 Executing an ATA Polling Command59934.10.2 Executing an ATA Interrupt Command59934.10.3 Aborting an ATA Command59934.10.4 CE-ATA Error Recovery59934.11 HSMCI Boot Operation Mode60034.11.1 Boot Procedure, Processor Mode60034.11.2 Boot Procedure DMA Mode60034.12 HSMCI Transfer Done Timings60134.12.1 Definition60134.12.2 Read Access60134.12.3 Write Access60134.13 Write Protection Registers60234.14 High Speed MultiMedia Card Interface (HSMCI) User Interface60334.14.1 HSMCI Control Register60434.14.2 HSMCI Mode Register60534.14.3 HSMCI Data Timeout Register60634.14.4 HSMCI SDCard/SDIO Register60734.14.5 HSMCI Argument Register60834.14.6 HSMCI Command Register60934.14.7 HSMCI Block Register61134.14.8 HSMCI Completion Signal Timeout Register61234.14.9 HSMCI Response Register61334.14.10 HSMCI Receive Data Register61434.14.11 HSMCI Transmit Data Register61534.14.12 HSMCI Status Register61634.14.13 HSMCI Interrupt Enable Register61934.14.14 HSMCI Interrupt Disable Register62134.14.15 HSMCI Interrupt Mask Register62334.14.16 HSMCI DMA Configuration Register62534.14.17 HSMCI Configuration Register62634.14.18 HSMCI Write Protect Mode Register62734.14.19 HSMCI Write Protect Status Register62834.14.20 HSMCI FIFOx Memory Aperture62935. Serial Peripheral Interface (SPI)63035.1 Description63035.2 Embedded Characteristics63035.3 Block Diagram63135.4 Application Block Diagram63135.5 Signal Description63235.6 Product Dependencies63235.6.1 I/O Lines63235.6.2 Power Management63235.6.3 Interrupt63335.6.4 Direct Memory Access Controller (DMAC)63335.7 Functional Description63335.7.1 Modes of Operation63335.7.2 Data Transfer63335.7.3 Master Mode Operations63535.7.3.1 Master Mode Block Diagram63635.7.3.2 Master Mode Flow Diagram63735.7.3.3 Clock Generation63835.7.3.4 Transfer Delays63835.7.3.5 Peripheral Selection63935.7.3.6 SPI Direct Access Memory Controller (DMAC)63935.7.3.7 Peripheral Chip Select Decoding64035.7.3.8 Peripheral Deselection without DMA64035.7.3.9 Peripheral Deselection with DMAC64135.7.3.10 Mode Fault Detection64235.7.4 SPI Slave Mode64235.7.5 Write Protected Registers64335.8 Serial Peripheral Interface (SPI) User Interface64435.8.1 SPI Control Register64535.8.2 SPI Mode Register64635.8.3 SPI Receive Data Register64835.8.4 SPI Transmit Data Register64935.8.5 SPI Status Register65035.8.6 SPI Interrupt Enable Register65135.8.7 SPI Interrupt Disable Register65235.8.8 SPI Interrupt Mask Register65335.8.9 SPI Chip Select Register65435.8.10 SPI Write Protection Mode Register65635.8.11 SPI Write Protection Status Register65736. Timer Counter (TC)65836.1 Description65836.2 Embedded Characteristics65936.3 Block Diagram66036.4 Pin Name List66136.5 Product Dependencies66136.5.1 I/O Lines66136.5.2 Power Management66136.5.3 Interrupt66136.6 Functional Description66236.6.1 TC Description66236.6.2 32-bit Counter66236.6.3 Clock Selection66236.6.4 Clock Control66436.6.5 TC Operating Modes66436.6.6 Trigger66536.6.7 Capture Operating Mode66536.6.8 Capture Registers A and B66536.6.9 Trigger Conditions66536.6.10 Waveform Operating Mode66736.6.11 Waveform Selection66736.6.11.1 WAVSEL = 0066936.6.11.2 WAVSEL = 1067036.6.11.3 WAVSEL = 0167136.6.11.4 WAVSEL = 1167236.6.12 External Event/Trigger Conditions67336.6.13 Output Controller67336.7 Timer Counter (TC) User Interface67436.7.1 TC Channel Control Register67536.7.2 TC Channel Mode Register: Capture Mode67636.7.3 TC Channel Mode Register: Waveform Mode67836.7.4 TC Counter Value Register68236.7.5 TC Register A68336.7.6 TC Register B68336.7.7 TC Register C68436.7.8 TC Status Register68536.7.9 TC Interrupt Enable Register68736.7.10 TC Interrupt Disable Register68836.7.11 TC Interrupt Mask Register68936.7.12 TC Block Control Register69036.7.13 TC Block Mode Register69137. Pulse Width Modulation Controller (PWM)69237.1 Description69237.2 Embedded characteristics69237.3 Block Diagram69337.4 I/O Lines Description69337.5 Product Dependencies69437.5.1 I/O Lines69437.5.2 Power Management69437.5.3 Interrupt Sources69437.6 Functional Description69537.6.1 PWM Clock Generator69537.6.2 PWM Channel69637.6.2.1 Block Diagram69637.6.2.2 Waveform Properties69637.6.3 PWM Controller Operations69937.6.3.1 Initialization69937.6.3.2 Source Clock Selection Criteria69937.6.3.3 Changing the Duty Cycle or the Period69937.6.3.4 Interrupts70037.7 Pulse Width Modulation Controller (PWM) User Interface70137.7.1 PWM Mode Register70237.7.2 PWM Enable Register70337.7.3 PWM Disable Register70337.7.4 PWM Status Register70437.7.5 PWM Interrupt Enable Register70537.7.6 PWM Interrupt Disable Register70637.7.7 PWM Interrupt Mask Register70737.7.8 PWM Interrupt Status Register70837.7.9 PWM Channel Mode Register70937.7.10 PWM Channel Duty Cycle Register71037.7.11 PWM Channel Period Register71137.7.12 PWM Channel Counter Register71237.7.13 PWM Channel Update Register71338. Two-wire Interface (TWI)71438.1 Description71438.2 Embedded Characteristics71538.3 List of Abbreviations71538.4 Block Diagram71638.5 Application Block Diagram71638.5.1 I/O Lines Description71638.6 Product Dependencies71738.6.1 I/O Lines71738.6.2 Power Management71738.6.3 Interrupt71738.7 Functional Description71838.7.1 Transfer Format71838.7.2 Modes of Operation71838.8 Master Mode71938.8.1 Definition71938.8.2 Application Block Diagram71938.8.3 Programming Master Mode71938.8.4 Master Transmitter Mode71938.8.5 Master Receiver Mode72138.8.6 Internal Address72338.8.6.1 7-bit Slave Addressing72338.8.6.2 10-bit Slave Addressing72438.8.7 Using the DMA Controller72438.8.7.1 Data Transmit with the DMA72438.8.7.2 Data Receive with the DMA72438.8.8 SMBUS Quick Command (Master Mode Only)72538.8.9 Read-write Flowcharts72538.9 Multi-master Mode73238.9.1 Definition73238.9.2 Different Multi-master Modes73238.9.2.1 TWI as Master Only73238.9.2.2 TWI as Master or Slave73238.10 Slave Mode73538.10.1 Definition73538.10.2 Application Block Diagram73538.10.3 Programming Slave Mode73538.10.4 Receiving Data73538.10.4.1 Read Sequence73538.10.4.2 Write Sequence73638.10.4.3 Clock Synchronization Sequence73638.10.4.4 General Call73638.10.5 Data Transfer73638.10.5.1 Read Operation73638.10.5.2 Write Operation73738.10.5.3 General Call73738.10.5.4 Clock Synchronization73838.10.5.5 Reversal after a Repeated Start74038.10.6 Read Write Flowcharts74138.11 Write Protection System74238.12 Two-wire Interface (TWI) User Interface74338.12.1 TWI Control Register74438.12.2 TWI Master Mode Register74638.12.3 TWI Slave Mode Register74738.12.4 TWI Internal Address Register74838.12.5 TWI Clock Waveform Generator Register74938.12.6 TWI Status Register75038.12.7 TWI Interrupt Enable Register75338.12.8 TWI Interrupt Disable Register75438.12.9 TWI Interrupt Mask Register75538.12.10 TWI Receive Holding Register75638.12.11 TWI Transmit Holding Register75738.12.12 TWI Write Protection Mode Register75838.12.13 TWI Write Protection Status Register75939. Universal Synchronous Asynchronous Receiver Transmitter (USART)76039.1 Description76039.2 Embedded Characteristics76139.3 Block Diagram76239.4 Application Block Diagram76339.5 I/O Lines Description76439.6 Product Dependencies76439.6.1 I/O Lines76439.6.2 Power Management76539.6.3 Interrupt76539.7 Functional Description76639.7.1 Baud Rate Generator76739.7.1.1 Baud Rate in Asynchronous Mode76739.7.1.2 Fractional Baud Rate in Asynchronous Mode76939.7.1.3 Baud Rate in Synchronous Mode or SPI Mode76939.7.1.4 Baud Rate in ISO 7816 Mode76939.7.2 Receiver and Transmitter Control77139.7.3 Synchronous and Asynchronous Modes77139.7.3.1 Transmitter Operations77139.7.3.2 Manchester Encoder77239.7.3.3 Asynchronous Receiver77439.7.3.4 Manchester Decoder77539.7.3.5 Radio Interface: Manchester Encoded USART Application77739.7.3.6 Synchronous Receiver77839.7.3.7 Receiver Operations77839.7.3.8 Parity77939.7.3.9 Multidrop Mode78039.7.3.10 Transmitter Timeguard78039.7.3.11 Receiver Time-out78139.7.3.12 Framing Error78239.7.3.13 Transmit Break78339.7.3.14 Receive Break78439.7.3.15 Hardware Handshaking78439.7.4 ISO7816 Mode78539.7.4.1 ISO7816 Mode Overview78539.7.4.2 Protocol T = 078539.7.4.3 Protocol T = 178639.7.5 IrDA Mode78739.7.5.1 IrDA Modulation78739.7.5.2 IrDA Baud Rate78839.7.5.3 IrDA Demodulator78939.7.6 RS485 Mode78939.7.7 SPI Mode79039.7.7.1 Modes of Operation79039.7.7.2 Baud Rate79139.7.7.3 Data Transfer79139.7.7.4 Receiver and Transmitter Control79239.7.7.5 Character Transmission79339.7.7.6 Character Reception79339.7.7.7 Receiver Timeout79339.7.8 LIN Mode79339.7.8.1 Modes of Operation79439.7.8.2 Baud Rate Configuration79439.7.8.3 Receiver and Transmitter Control79439.7.8.4 Character Transmission79439.7.8.5 Character Reception79439.7.8.6 Header Transmission (Master Node Configuration)79439.7.8.7 Header Reception (Slave Node Configuration)79539.7.8.8 Slave Node Synchronization79639.7.8.9 Identifier Parity79839.7.8.10 Node Action79839.7.8.11 Response Data Length79939.7.8.12 Checksum79939.7.8.13 Frame Slot Mode79939.7.8.14 LIN Errors80039.7.8.15 LIN Frame Handling80139.7.8.16 LIN Frame Handling With The DMAC80439.7.8.17 Wake-up Request80639.7.8.18 Bus Idle Time-out80639.7.9 Test Modes80739.7.9.1 Normal Mode80739.7.9.2 Automatic Echo Mode80739.7.9.3 Local Loopback Mode80739.7.9.4 Remote Loopback Mode80839.7.10 Write Protection Registers80939.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface81039.8.1 USART Control Register81139.8.2 USART Control Register (SPI_MODE)81339.8.3 USART Mode Register81539.8.4 USART Mode Register (SPI_MODE)81839.8.5 USART Interrupt Enable Register82039.8.6 USART Interrupt Enable Register (SPI_MODE)82139.8.7 USART Interrupt Enable Register (LIN_MODE)82239.8.8 USART Interrupt Disable Register82339.8.9 USART Interrupt Disable Register (SPI_MODE)82439.8.10 USART Interrupt Disable Register (LIN_MODE)82539.8.11 USART Interrupt Mask Register82639.8.12 USART Interrupt Mask Register (SPI_MODE)82739.8.13 USART Interrupt Mask Register (LIN_MODE)82839.8.14 USART Channel Status Register82939.8.15 USART Channel Status Register (SPI_MODE)83139.8.16 USART Channel Status Register (LIN_MODE)83239.8.17 USART Receive Holding Register83439.8.18 USART Transmit Holding Register83539.8.19 USART Baud Rate Generator Register83639.8.20 USART Receiver Time-out Register83739.8.21 USART Transmitter Timeguard Register83839.8.22 USART FI DI RATIO Register83939.8.23 USART Number of Errors Register84039.8.24 USART IrDA FILTER Register84139.8.25 USART Manchester Configuration Register84239.8.26 USART LIN Mode Register84439.8.27 USART LIN Identifier Register84639.8.28 USART LIN Baud Rate Register84739.8.29 USART Write Protect Mode Register84839.8.30 USART Write Protect Status Register84940. Universal Asynchronous Receiver Transmitter (UART)85040.1 Description85040.2 Embedded Characteristics85040.3 Block Diagram85140.4 Product Dependencies85240.4.1 I/O Lines85240.4.2 Power Management85240.4.3 Interrupt Source85240.5 UART Operations85240.5.1 Baud Rate Generator85240.5.2 Receiver85340.5.2.1 Receiver Reset, Enable and Disable85340.5.2.2 Start Detection and Data Sampling85340.5.2.3 Receiver Ready85440.5.2.4 Receiver Overrun85440.5.2.5 Parity Error85440.5.2.6 Receiver Framing Error85540.5.3 Transmitter85540.5.3.1 Transmitter Reset, Enable and Disable85540.5.3.2 Transmit Format85540.5.3.3 Transmitter Control85640.5.4 DMA Support85640.5.5 Test Modes85640.6 Universal Asynchronous Receiver Transmitter (UART) User Interface85840.6.1 UART Control Register85940.6.2 UART Mode Register86040.6.3 UART Interrupt Enable Register86140.6.4 UART Interrupt Disable Register86240.6.5 UART Interrupt Mask Register86340.6.6 UART Status Register86440.6.7 UART Receiver Holding Register86540.6.8 UART Transmit Holding Register86640.6.9 UART Baud Rate Generator Register86741. Controller Area Network (CAN) Programmer Datasheet86841.1 Description86841.2 Embedded Characteristics86941.3 Block Diagram87041.4 Application Block Diagram87041.5 I/O Lines Description87141.6 Product Dependencies87141.6.1 I/O Lines87141.6.2 Power Management87141.6.3 Interrupt87141.7 CAN Controller Features87241.7.1 CAN Protocol Overview87241.7.2 Mailbox Organization87241.7.2.1 Message Acceptance Procedure87241.7.2.2 Receive Mailbox87341.7.2.3 Transmit Mailbox87441.7.3 Time Management Unit87441.7.4 CAN 2.0 Standard Features87541.7.4.1 CAN Bit Timing Configuration87541.7.4.2 Error Detection87841.7.4.3 Overload87941.7.5 Low-power Mode87941.7.5.1 Enabling Low-power Mode87941.7.5.2 Disabling Low-power Mode88041.8 Functional Description88241.8.1 CAN Controller Initialization88241.8.2 CAN Controller Interrupt Handling88341.8.3 CAN Controller Message Handling88341.8.3.1 Receive Handling88341.8.3.2 Transmission Handling88741.8.3.3 Remote Frame Handling88841.8.4 CAN Controller Timing Modes89041.8.4.1 Timestamping Mode89041.8.4.2 Time Triggered Mode89041.8.5 Write Protected Registers89341.9 Controller Area Network (CAN) User Interface89441.9.1 CAN Mode Register89541.9.2 CAN Interrupt Enable Register89641.9.3 CAN Interrupt Disable Register89841.9.4 CAN Interrupt Mask Register90041.9.5 CAN Status Register90241.9.6 CAN Baudrate Register90541.9.7 CAN Timer Register90641.9.8 CAN Timestamp Register90741.9.9 CAN Error Counter Register90841.9.10 CAN Transfer Command Register90941.9.11 CAN Abort Command Register91041.9.12 CAN Write Protection Mode Register91141.9.13 CAN Write Protection Status Register91241.9.14 CAN Message Mode Register91341.9.15 CAN Message Acceptance Mask Register91441.9.16 CAN Message ID Register91541.9.17 CAN Message Family ID Register91641.9.18 CAN Message Status Register91741.9.19 CAN Message Data Low Register92041.9.20 CAN Message Data High Register92141.9.21 CAN Message Control Register92242. Analog-to-Digital Converter (ADC)92442.1 Description92442.2 Embedded Characteristics92542.3 Block Diagram92642.4 Signal Description92642.5 Product Dependencies92742.5.1 Power Management92742.5.2 Interrupt Sources92742.5.3 Analog Inputs92742.5.4 I/O Lines92742.5.5 Timer Triggers92742.5.6 Conversion Performances92742.6 Functional Description92842.6.1 Analog-to-digital Conversion92842.6.2 Conversion Reference92842.6.3 Conversion Resolution92842.6.4 Conversion Results92942.6.5 Conversion Triggers93142.6.6 Sleep Mode and Conversion Sequencer93142.6.7 Comparison Window93242.6.8 ADC Timings93242.7 Touchscreen93242.7.1 Touchscreen Mode93242.7.2 4-wire Resistive Touchscreen Principles93242.7.3 4-wire Position Measurement Method93342.7.4 4-wire Pressure Measurement Method93442.7.5 5-wire Resistive Touchscreen Principles93542.7.6 5-wire Position Measurement Method93642.7.7 Sequence and Noise Filtering93742.7.8 Measured Values, Registers and Flags93842.7.9 Pen Detect Method93842.7.10 Buffer Structure94042.7.10.1 Classical ADC Channels Only94042.7.10.2 TouchScreen Channels Only94042.7.10.3 Interleaved Channels94242.7.10.4 Pen Detection Status94442.7.11 Write Protected Registers94542.8 Analog-to-Digital Converter (ADC) User Interface94642.8.1 ADC Control Register94742.8.2 ADC Mode Register94842.8.3 ADC Channel Sequence 1 Register95042.8.4 ADC Channel Sequence 2 Register95142.8.5 ADC Channel Enable Register95242.8.6 ADC Channel Disable Register95342.8.7 ADC Channel Status Register95442.8.8 ADC Last Converted Data Register95542.8.9 ADC Interrupt Enable Register95642.8.10 ADC Interrupt Disable Register95742.8.11 ADC Interrupt Mask Register95842.8.12 ADC Interrupt Status Register95942.8.13 ADC Overrun Status Register96142.8.14 ADC Extended Mode Register96242.8.15 ADC Compare Window Register96342.8.16 ADC Channel Data Register96442.8.17 ADC Analog Control Register96542.8.18 ADC Touchscreen Mode Register96642.8.19 ADC Touchscreen X Position Register96842.8.20 ADC Touchscreen Y Position Register96942.8.21 ADC Touchscreen Pressure Register97042.8.22 ADC Trigger Register97142.8.23 ADC Write Protect Mode Register97242.8.24 ADC Write Protect Status Register97343. Software Modem Device (SMD)97443.1 Description97443.2 Embedded Characteristics97443.3 Block Diagram97544. Synchronous Serial Controller (SSC)97644.1 Description97644.2 Embedded Characteristics97644.3 Block Diagram97744.4 Application Block Diagram97744.5 Pin Name List97844.6 Product Dependencies97844.6.1 I/O Lines97844.6.2 Power Management97844.6.3 Interrupt97844.7 Functional Description97944.7.1 Clock Management98044.7.1.1 Clock Divider98044.7.1.2 Transmitter Clock Management98144.7.1.3 Receiver Clock Management98144.7.1.4 Serial Clock Ratio Considerations98244.7.2 Transmitter Operations98244.7.3 Receiver Operations98344.7.4 Start98444.7.5 Frame Sync98644.7.5.1 Frame Sync Data98644.7.5.2 Frame Sync Edge Detection98644.7.6 Receive Compare Modes98644.7.6.1 Compare Functions98644.7.7 Data Format98744.7.8 Loop Mode98844.7.9 Interrupt98844.8 SSC Application Examples99044.8.1 Write Protection Registers99244.9 Synchronous Serial Controller (SSC) User Interface99344.9.1 SSC Control Register99444.9.2 SSC Clock Mode Register99544.9.3 SSC Receive Clock Mode Register99644.9.4 SSC Receive Frame Mode Register99844.9.5 SSC Transmit Clock Mode Register100044.9.6 SSC Transmit Frame Mode Register100244.9.7 SSC Receive Holding Register100444.9.8 SSC Transmit Holding Register100444.9.9 SSC Receive Synchronization Holding Register100544.9.10 SSC Transmit Synchronization Holding Register100544.9.11 SSC Receive Compare 0 Register100644.9.12 SSC Receive Compare 1 Register100644.9.13 SSC Status Register100744.9.14 SSC Interrupt Enable Register100944.9.15 SSC Interrupt Disable Register101044.9.16 SSC Interrupt Mask Register101144.9.17 SSC Write Protect Mode Register101244.9.18 SSC Write Protect Status Register101345. Ethernet MAC 10/100 (EMAC)101445.1 Description101445.2 Embedded Characteristics101445.3 Block Diagram101545.4 Functional Description101645.4.1 Clock101645.4.2 Memory Interface101645.4.2.1 FIFO101745.4.2.2 Receive Buffers101745.4.2.3 Transmit Buffer101945.4.3 Transmit Block102045.4.4 Pause Frame Support102145.4.5 Receive Block102145.4.6 Address Checking Block102145.4.7 Broadcast Address102245.4.8 Hash Addressing102345.4.9 Copy All Frames (or Promiscuous Mode)102345.4.10 Type ID Checking102345.4.11 VLAN Support102345.4.12 PHY Maintenance102445.4.13 Physical Interface102445.4.13.1 RMII Transmit and Receive Operation102445.5 Programming Interface102545.5.1 Initialization102545.5.1.1 Configuration102545.5.1.2 Receive Buffer List102545.5.1.3 Transmit Buffer List102545.5.1.4 Address Matching102645.5.1.5 Interrupts102645.5.1.6 Transmitting Frames102645.5.1.7 Receiving Frames102745.6 Ethernet MAC 10/100 (EMAC) User Interface102845.6.1 Network Control Register103045.6.2 Network Configuration Register103245.6.3 Network Status Register103445.6.4 Transmit Status Register103545.6.5 Receive Buffer Queue Pointer Register103645.6.6 Transmit Buffer Queue Pointer Register103745.6.7 Receive Status Register103845.6.8 Interrupt Status Register103945.6.9 Interrupt Enable Register104145.6.10 Interrupt Disable Register104345.6.11 Interrupt Mask Register104545.6.12 PHY Maintenance Register104745.6.13 Pause Time Register104845.6.14 Hash Register Bottom104945.6.15 Hash Register Top105045.6.16 Specific Address 1 Bottom Register105145.6.17 Specific Address 1 Top Register105245.6.18 Specific Address 2 Bottom Register105345.6.19 Specific Address 2 Top Register105445.6.20 Specific Address 3 Bottom Register105545.6.21 Specific Address 3 Top Register105645.6.22 Specific Address 4 Bottom Register105745.6.23 Specific Address 4 Top Register105845.6.24 Type ID Checking Register105945.6.25 User Input/Output Register106045.6.26 EMAC Statistic Registers106145.6.26.1 Pause Frames Received Register106245.6.26.2 Frames Transmitted OK Register106345.6.26.3 Single Collision Frames Register106445.6.26.4 Multicollision Frames Register106545.6.26.5 Frames Received OK Register106645.6.26.6 Frames Check Sequence Errors Register106745.6.26.7 Alignment Errors Register106845.6.26.8 Deferred Transmission Frames Register106945.6.26.9 Late Collisions Register107045.6.26.10 Excessive Collisions Register107145.6.26.11 Transmit Underrun Errors Register107245.6.26.12 Carrier Sense Errors Register107345.6.26.13 Receive Resource Errors Register107445.6.26.14 Receive Overrun Errors Register107545.6.26.15 Receive Symbol Errors Register107645.6.26.16 Excessive Length Errors Register107745.6.26.17 Receive Jabbers Register107845.6.26.18 Undersize Frames Register107945.6.26.19 SQE Test Errors Register108045.6.26.20 Received Length Field Mismatch Register108146. LCD Controller (LCDC)108246.1 Description108246.2 Embedded Characteristics108246.3 Block Diagram108346.4 I/O Lines Description108446.5 Product Dependencies108546.5.1 I/O Lines108546.5.2 Power Management108646.5.3 Interrupt Sources108646.6 Functional Description108746.6.1 Timing Engine Configuration108746.6.1.1 Pixel Clock Period Configuration108746.6.1.2 Horizontal and Vertical Synchronization Configuration108746.6.1.3 Timing Engine Power Up Software Operation108846.6.1.4 Timing Engine Power Down Software Operation108846.6.2 DMA Software Operations108846.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure108846.6.2.2 Programming a DMA Channel108846.6.2.3 Disabling a DMA channel108946.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor108946.6.2.5 DMA Interrupt Generation108946.6.2.6 DMA Address Alignment Requirements108946.6.3 Display Software Configuration109046.6.3.1 System Bus Access Attributes109046.6.3.2 Color Attributes109046.6.3.3 Window Position, Size, Scaling and Striding Attributes109146.6.3.4 Overlay Blender Attributes109246.6.3.5 Window Attributes Software Operation109246.6.4 RGB Frame Buffer Memory Bitmap109246.6.4.1 1 bpp Through Color Lookup Table109246.6.4.2 2 bpp Through Color Lookup Table109246.6.4.3 4 bpp Through Color Lookup Table109246.6.4.4 8 bpp Through Color Lookup Table109246.6.4.5 12 bpp Memory Mapping, RGB 4:4:4109346.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4109346.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4109346.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5109346.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5109346.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6109346.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6109346.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6109446.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6109446.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8109446.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8109446.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8109546.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8109546.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8109546.6.5 YUV Frame Buffer Memory Mapping109546.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping109546.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping109546.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping109646.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping109646.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping109646.6.5.6 4:2:0 Semiplanar Frame Buffer memory Mapping109746.6.6 Chrominance Upsampling Unit109846.6.6.1 Chrominance Upsampling Algorithm110246.6.7 Line and Pixel Striding110246.6.7.1 Line Striding110246.6.7.2 Pixel Striding110246.6.8 Color Space Conversion Unit110246.6.9 Two Dimension Scaler110346.6.9.1 Horizontal Scaler110346.6.9.2 Vertical Scaler110346.6.10 Hardware Cursor110346.6.11 Color Combine Unit110346.6.11.1 Window Overlay110346.6.11.2 Overlay Blending110546.6.11.3 Global Alpha Blender110646.6.11.4 Window Blending110646.6.11.5 Color Keying110746.6.12 LCD Overall Performance110746.6.12.1 Color Lookup Table (CLUT)110746.6.12.2 RGB Mode Fetch Performance110846.6.12.3 YUV Mode Fetch Performance110846.6.13 Output Timing Generation111046.6.13.1 Active Display Timing Mode111046.6.14 Output Format111446.6.14.1 Active Mode Output Pin Assignment111446.7 LCD Controller (LCDC) User Interface111546.7.1 LCD Controller Configuration Register 0111946.7.2 LCD Controller Configuration Register 1112046.7.3 LCD Controller Configuration Register 2112146.7.4 LCD Controller Configuration Register 3112246.7.5 LCD Controller Configuration Register 4112346.7.6 LCD Controller Configuration Register 5112446.7.7 LCD Controller Configuration Register 6112646.7.8 LCD Controller Enable Register112746.7.9 LCD Controller Disable Register112846.7.10 LCD Controller Status Register112946.7.11 LCD Controller Interrupt Enable Register113046.7.12 LCD Controller Interrupt Disable Register113146.7.13 LCD Controller Interrupt Mask Register113246.7.14 LCD Controller Interrupt Status Register113346.7.15 Base Layer Channel Enable Register113446.7.16 Base Layer Channel Disable Register113546.7.17 Base Layer Channel Status Register113646.7.18 Base Layer Interrupt Enable Register113746.7.19 Base Layer Interrupt Disable Register113846.7.20 Base Layer Interrupt Mask Register113946.7.21 Base Layer Interrupt Status Register114046.7.22 Base Layer Head Register114146.7.23 Base Layer Address Register114246.7.24 Base Layer Control Register114346.7.25 Base Layer Next Register114446.7.26 Base Layer Configuration 0 Register114546.7.27 Base Layer Configuration 1 Register114646.7.28 Base Layer Configuration 2 Register114746.7.29 Base Layer Configuration 3 Register114846.7.30 Base Layer Configuration 4 Register114946.7.31 Overlay 1 Layer Channel Enable Register115046.7.32 Overlay 1 Layer Channel Disable Register115146.7.33 Overlay 1 Layer Channel Status Register115246.7.34 Overlay 1 Layer Interrupt Enable Register115346.7.35 Overlay 1 Layer Interrupt Disable Register115446.7.36 Overlay 1 Layer Interrupt Mask Register115546.7.37 Overlay 1 Layer Interrupt Status Register115646.7.38 Overlay 1 Layer Head Register115746.7.39 Overlay 1 Layer Address Register115846.7.40 Overlay 1 Layer Control Register115946.7.41 Overlay 1 Layer Next Register116046.7.42 Overlay 1 Layer Configuration 0 Register116146.7.43 Overlay 1 Layer Configuration 1 Register116246.7.44 Overlay 1 Layer Configuration 2 Register116346.7.45 Overlay 1 Layer Configuration 3 Register116446.7.46 Overlay 1 Layer Configuration 4 Register116546.7.47 Overlay 1 Layer Configuration 5 Register116646.7.48 Overlay 1 Layer Configuration 6 Register116746.7.49 Overlay 1 Layer Configuration 7 Register116846.7.50 Overlay 1 Layer Configuration 8 Register116946.7.51 Overlay1 Layer Configuration 9 Register117046.7.52 High End Overlay Layer Channel Enable Register117246.7.53 High End Overlay Layer Channel Disable Register117346.7.54 High End Overlay Layer Channel Status Register117446.7.55 High End Overlay Layer Interrupt Enable Register117546.7.56 High End Overlay Layer Interrupt Disable Register117746.7.57 High End Overlay Layer Interrupt Mask Register117946.7.58 High End Overlay Layer Interrupt Status Register118146.7.59 High End Overlay Layer Head Register118346.7.60 High End Overlay Layer Address Register118446.7.61 High End Overlay Layer Control Register118546.7.62 High End Overlay Layer Next Register118646.7.63 High End Overlay Layer U-UV Head Register118746.7.64 High End Overlay Layer U-UV Address Register118846.7.65 High End Overlay Layer U-UV Control Register118946.7.66 High End Overlay Layer U-UV Next Register119046.7.67 High End Overlay Layer V Head Register119146.7.68 High End Overlay Layer V Address Register119246.7.69 High End Overlay Layer V Control Register119346.7.70 High End Overlay Layer V Next Register119446.7.71 High End Overlay Layer Configuration 0 Register119546.7.72 High End Overlay Layer Configuration 1 Register119746.7.73 High End Overlay Layer Configuration 2 Register119946.7.74 High End Overlay Layer Configuration 3 Register120046.7.75 High End Overlay Layer Configuration 4 Register120146.7.76 High End Overlay Layer Configuration 5 Register120246.7.77 High End Overlay Layer Configuration 6 Register120346.7.78 High End Overlay Layer Configuration 7 Register120446.7.79 High End Overlay Layer Configuration 8 Register120546.7.80 High End Overlay Layer Configuration 9 Register120646.7.81 High End Overlay Layer Configuration 10 Register120746.7.82 High End Overlay Layer Configuration 11 Register120846.7.83 High End Overlay Layer Configuration 12 Register120946.7.84 High End Overlay Layer Configuration 13 Register121146.7.85 High End Overlay Layer Configuration 14 Register121246.7.86 High End Overlay Layer Configuration 15 Register121346.7.87 High End Overlay Layer Configuration 16 Register121446.7.88 Hardware Cursor Layer Channel Enable Register121546.7.89 Hardware Cursor Layer Channel Disable Register121646.7.90 Hardware Cursor Layer Channel Status Register121746.7.91 Hardware Cursor Layer Interrupt Enable Register121846.7.92 Hardware Cursor Layer Interrupt Disable Register121946.7.93 Hardware Cursor Layer Interrupt Mask Register122046.7.94 Hardware Cursor Layer Interrupt Status Register122146.7.95 Hardware Cursor Layer Head Register122246.7.96 Hardware Cursor Layer Address Register122346.7.97 Hardware Cursor Layer Control Register122446.7.98 Hardware Cursor Layer Next Register122546.7.99 Hardware Cursor Layer Configuration 0 Register122646.7.100 Hardware Cursor Layer Configuration 1 Register122746.7.101 Hardware Cursor Layer Configuration 2 Register122846.7.102 Hardware Cursor Layer Configuration 3 Register122946.7.103 Hardware Cursor Layer Configuration 4 Register123046.7.104 Hardware Cursor Layer Configuration 6 Register123146.7.105 Hardware Cursor Layer Configuration 7 Register123246.7.106 Hardware Cursor Layer Configuration 8 Register123346.7.107 Hardware Cursor Layer Configuration 9 Register123446.7.108 Base CLUT Register x Register123646.7.109 Overlay 1 CLUT Register x Register123746.7.110 High End Overlay CLUT Register x Register123846.7.111 Hardware Cursor CLUT Register x Register123947. Electrical Characteristics124047.1 Absolute Maximum Ratings124047.2 DC Characteristics124147.3 Power Consumption124247.3.1 Power Consumption versus Modes124247.4 Clock Characteristics124447.4.1 Processor Clock Characteristics124447.4.2 Master Clock Characteristics124447.5 Main Oscillator Characteristics124447.5.1 Crystal Oscillator Characteristics124547.5.2 XIN Clock Characteristics124547.6 12 MHz RC Oscillator Characteristics124647.7 32 kHz Oscillator Characteristics124647.7.1 32 kHz Crystal Characteristics124747.7.2 XIN32 Clock Characteristics124747.8 32 kHz RC Oscillator Characteristics124747.9 PLL Characteristics124847.9.1 UTMI PLL Characteristics124847.10 I/Os124947.11 USB HS Characteristics124947.12 USB Transceiver Characteristics125047.13 Analog-to-Digital Converter (ADC)125147.14 POR Characteristics125347.14.1 Core Power Supply POR Characteristics125347.14.2 Backup Power Supply POR Characteristics125347.15 Power Sequence Requirements125447.15.1 Power-Up Sequence125447.16 SMC Timings125547.16.1 Timing Conditions125547.16.2 Timing Extraction125547.16.2.1 Zero Hold Mode Restrictions125547.16.2.2 Read Timings125647.16.2.3 Write Timings125747.17 DDRSDRC Timings125847.18 Peripheral Timings125947.18.1 SPI125947.18.1.1 Maximum SPI Frequency125947.18.1.2 Timing Conditions125947.18.1.3 Timing Extraction125947.18.2 SSC126347.18.2.1 Timing conditions126347.18.2.2 Timing Extraction126347.18.3 HSMCI126747.18.4 EMAC126747.18.4.1 Timing conditions126747.18.4.2 Timing constraints126747.18.4.3 RMII Mode126847.18.5 USART in SPI Mode Timings126947.18.5.1 T iming conditions126947.18.5.2 Timing extraction126947.19 Two-wire Interface Characteristics127248. Mechanical Overview127448.1 217-ball BGA Package127448.2 Marking127549. SAM9X35 Ordering Information127650. SAM9X35 Errata127750.1 External Bus Interface (EBI)127750.1.1 EBI: Data lines are Hi-Z after reset127750.2 Reset Controller (RSTC)127750.2.1 RSTC: Reset during SDRAM Accesses127750.3 Static Memory Controller (SMC)127750.3.1 SMC: SMC DELAY I/O Registers are write-only127750.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)127750.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL127750.5 Timer Counter (TC)127850.5.1 TC: The TIOA5 signal is not well connected127850.6 LCD Controller (LCDC)127850.6.1 LCDC: LCDC PWM is not usable127850.7 Boot Strategy127950.7.1 NAND Flash Boot Detection using ONFI parameters does not work127950.8 Real Time Clock (RTC)127950.8.1 RTC: Interrupt Mask Register cannot be used1279Revision History1280Table of Contents1292Size: 5.46 MBPages: 1301Language: EnglishOpen manual
