Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

Product codes
AT91SAM9X35-EK
Page of 1301
1152
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.7.33 Overlay 1 Layer Channel Status Register
Name: 
LCDC_OVRCHSR1
Address:
0xF8038108
Access: 
Read-only
Reset: 
0x00000000
• CHSR: Channel Status Register
When set to one, this field disables the layer at the end of the current frame.
• UPDATESR: Update Overlay Attributes In Progress
When set to one, this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add to Queue Pending Register
When set to one, this bit indicates that the head pointer is still pending.
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A2QSR
UPDATESR
CHSR