Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
1255
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
47.16 SMC Timings
47.16.1 Timing Conditions
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads.
In the following tables, t
CPMCK
is MCK period.
47.16.2 Timing Extraction
47.16.2.1 Zero Hold Mode Restrictions
Table 47-31. Capacitance Load
Supply
Corner
Max
Min
3.3V
50 pF
5 pF
1.8V
30 pF
5 pF
Table 47-32. Zero Hold Mode Use Maximum System Clock Frequency (MCK)
Symbol
Parameter
Max
Unit
VDDIOM supply 1.8V
VDDIOM supply 3.3V
f
max
MCK frequency
66
66
MHz