Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

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SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral,
the user just needs to write the READ command and the peripheral ID.

Code Example to select divider 8 for peripheral 2 and enable its clock: 

write_register(PMC_PCR,0x010031002)

Code Example to read the divider of peripheral 4: 

write_register(PMC_PCR,0x00000004)

read_register(PMC_PCR)

When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled
after a reset.

In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.

The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally,
the bit number corresponds to the interrupt source number assigned to the peripheral.

The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the
PMC_PCKx registers.

PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL
output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2
between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. 

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR
(System Clock Status Register).

Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change
is actually performed. 

1.

Enabling the 12 MHz Main Oscillator:

The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be 
advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the 
CKGR_MOR register.

Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be 
set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associ-
ated interrupt to MOSCS has been enabled in the PMC_IER register.

2.

Setting PLLA and divider:

All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register.

The DIVA field is used to control the divider itself. A value between 0 and 255 can be programmed. Divider output 
is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is 
turned off.

The OUTA field is used to select the PLLA output frequency range.

The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA is 
set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by 
(MULA + 1).