Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
217
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
These Additional Modes are:
Rising Edge Detection
Falling Edge Detection
Low Level Detection
High Level Detection
In order to select an Additional Interrupt Mode:
The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge
Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection.
The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection.
The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in the set
of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level
Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR), Edge or High
or Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible
through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level
Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR), Edge or High
or Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible
through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is
set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the
thirty-two channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the
thirty-two channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that
are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 23-7. Event Detector on Input Lines (Figure represents line 0)
23.5.10.1Example
If generating an interrupt is required on the following:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low Level on PIO line 3
High Level on PIO line 4
High Level on PIO line 5
Falling edge on PIO line 6
Event Detector
0
1
0
1
1
0
0
1
Edge
Detector
Falling Edge
Detector
Rising Edge
Detector
PIO_FELLSR[0]
PIO_FRLHSR[0]
PIO_REHLSR[0]
Low Level
Detector
High Level
Detector
PIO_ESR[0]
PIO_ELSR[0]
PIO_LSR[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
PIO_AIMER[0]
Event detection on line 0
Resynchronized input on line 0