Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

Product codes
AT91SAM9X35-EK
Page of 1301
281
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
25.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access
from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired,
and shown as “–” in the following table.
25.3 Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several
memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using
different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap
action for every master independently.
25.4 Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from masters.
This mechanism reduces latency at first access of a burst, or single transfer, as long as the slave is free from any other
master access, but does not provide any benefit as soon as the slave is continuously accessed by more than one master,
since arbitration is pipelined and has no negative effect on the slave bandwidth or access latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default
master. A slave can be associated with three kinds of default masters:
No default master
Last access master
Fixed default master
To change from one type of default master to another, the Bus Matrix user interface provides the Slave Configuration
Registers, one for every slave, that set a default master for each slave. The Slave Configuration Register contains two
fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no
Table 25-3. Master to Slave Access
Masters
0
1
2 & 3
4 & 5
6
7
8
9
10
11
Slaves
ARM926 
Instr.
ARM926 
Data
DMA 0
DMA 1
USB 
Device HS 
DMA
USB Host 
HS EHCI
USB Host 
HS OHCI LCD DMA
EMAC 
DMA
Reserved
0
Internal SRAM
X
X
X
X
X
X
X
X
X
X
1
Internal ROM
X
X
X
X
2
SMD
X
X
X
3
USB Device High 
Speed DPR
USB Host EHCI 
registers
USB Host OHCI 
registers
X
X
4
External Bus 
Interface
X
X
X
X
X
X
X
X
X
X
5
DDR2 Port 1
X
X
6
DDR2 Port 2
X
X
7
DDR2 Port 3
X
8
Peripheral Bridge 0
X
X
X
X
9
Peripheral Bridge 1
X
X
X
X