Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

289

SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

MATRIX_SCFG0...MATRIX_SCFG9

0xFFFFDE40 [0], 0xFFFFDE44 [1], 0xFFFFDE48 [2], 0xFFFFDE4C [3], 0xFFFFDE50 [4], 0xFFFFDE54 [5], 

0xFFFFDE58 [6], 0xFFFFDE5C [7], 0xFFFFDE60 [8], 0xFFFFDE64 [9]

Read/Write 

This register can only be written if the WPEN bit is cleared in the 

.

When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let another 
master access this slave. If another master is requesting the slave bus, then the current master burst is broken.

If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT.

This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave 
access or in the particular case of a master performing back-to-back undefined length bursts indefinitely freezing the arbitration.

This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing 
any data transfer. The default maximum value is usually an optimal conservative choice.

In most cases this feature is not needed and should be disabled for power saving. See 

.

0: No Default Master

At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.

This results in a one-clock cycle latency for the first access of a burst transfer or for a single access.

1: Last Default Master

At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having 
accessed it.

This results in not having a one-clock cycle latency when the last master tries to access the slave again.

2: Fixed Default Master

At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number 
that has been written in the FIXED_DEFMSTR field.

This results in not having a one-clock cycle latency when the fixed master tries to access the slave again.

This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master 
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

FIXED_DEFMSTR

DEFMSTR_TYPE

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

SLOT_CYCLE

7

6

5

4

3

2

1

0

SLOT_CYCLE