Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
389
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Figure 29-33.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
29.14 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE
register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned
to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the
page in memory, the LSB of address define the address of the data in the page as detailed in
to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the
page in memory, the LSB of address define the address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
pa
) takes longer than the subsequent accesses to the
page (t
sa
. When in page mode, the SMC enables the user to define different read timings for
the first access within one page, and next accesses within the page.
Notes: 1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
A
[25:2]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
2
3
2
NORMAL MODE WRITE
IDLE STATE
Reload Configuration
Wait State
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS2, NBS3,
A0,A1
Table 29-6. Page Address and Data Address within a Page
Page Size
Data Address in the Page
4 bytes
A[25:2]
A[1:0]
8 bytes
A[25:3]
A[2:0]
16 bytes
A[25:4]
A[3:0]
32 bytes
A[25:5]
A[4:0]