Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
452
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the
next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a
descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is
enabled.
next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a
descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is
enabled.
Replay – The DMAC automatically reloads the channel registers at the end of each buffers to the value when the
channel was first enabled.
channel was first enabled.
Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the end of the
previous buffer.
previous buffer.
Picture-in-Picture Mode: DMAC contains a Picture-in-Picture mode support. When this mode is enabled, addresses are
automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined
boundary.
automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined
boundary.
illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory.
A user defined start address is defined at Picture_start_address. The incremented value is set to memory_hole_size =
image_width - picture_width, and the boundary is set to picture_width.
image_width - picture_width, and the boundary is set to picture_width.
Figure 31-4. Picture-In-Picture Mode Support
Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the
master bus interface for the duration of a DMAC transfer, buffer, or chunk.
master bus interface for the duration of a DMAC transfer, buffer, or chunk.
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the
duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus
locking at a minimum.
duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus
locking at a minimum.
31.4.2 Memory Peripherals
shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no
handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the
channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not
having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once
the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus
until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking
interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access
the peripheral without the peripheral inserting wait states onto the bus.
channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not
having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once
the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus
until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking
interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access
the peripheral without the peripheral inserting wait states onto the bus.
DMAC PIP transfers