Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
513
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
32.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the
endpoint.
endpoint.
Algorithm Description for Each Packet:
The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write
access to the DPR.
access to the DPR.
The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window.
The application sets TXRDY flag in the UDPHS_EPTSETSTAx register.
The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can
be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set
by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set
by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This
means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait
that at least one bank is free.
that at least one bank is free.
The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the
application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the
TXRDY bit in the UDPHS_EPTSETSTAx register.
TXRDY bit in the UDPHS_EPTSETSTAx register.
The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.
A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register.
32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to
the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer
types except control transfer.
the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer
types except control transfer.
Example DMA configuration:
1.
Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred.
2.
Enable the interrupt of the DMA in UDPHS_IEN
3.
Program UDPHS_ DMACONTROLx:
Size of buffer to send: size of the buffer to be sent to the host.
END_B_EN: The endpoint can validate the packet (according to the values programmed in the
AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See
AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See
END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0.
CHANN_ENB: Run and stop at end of buffer
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means
that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.