Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
521
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
The FRCESTALL command bit is unused for an isochonous endpoint.
Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in
UDPHS_EPTSTAx register is updated.
UDPHS_EPTSTAx register is updated.
32.6.10.15 STALL
STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING
transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not
supported.
transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not
supported.
OUT
To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been
set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.
set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.
IN
Set the FRCESTALL bit in UDPHS_EPTSETSTAx register.
Figure 32-17.Stall Handshake Data OUT Transfer
Figure 32-18.Stall Handshake Data IN Transfer
32.6.11 Speed Identification
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.
32.6.12 USB V2.0 High Speed Global Interrupt
Interrupts are defined in
(UDPHS_INTSTA).
Token OUT
Stall PID
Data OUT
USB Bus
Packets
Packets
Cleared by Firmware
Set by Firmware
FRCESTALL
STALL_SNT
Set by Hardware
Interrupt Pending
Cleared by Firmware
Token IN
Stall PID
USB Bus
Packets
Packets
Cleared by Firmware
Set by Firmware
FRCESTALL
STALL_SNT
Set by Hardware
Cleared by Firmware
Interrupt Pending