Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
551
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
32.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)
Name:
UDPHS_EPTCTLx [x=0..6] (ISOENDPT)
Address:
0xF803C10C [0], 0xF803C12C [1], 0xF803C14C [2], 0xF803C16C [3], 0xF803C18C [4], 0xF803C1AC [5],
0xF803C1CC [6]
Access:
Read-only
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hard-
ware or UDPHS bus reset and participate in the device configuration.
ware or UDPHS bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
For IN Transfer:
If this bit is set, then the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full
and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user
wants to send a Zero Length Packet by software.
wants to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when
the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx reg-
ister END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.
the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx reg-
ister END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.
The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer
by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the
remaining data bank(s).
by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the
remaining data bank(s).
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN reg-
ister EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer
completion is needed.
ister EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer
completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally com-
pleted, but the new DMA packet transfer is not started (not requested).
pleted, but the new DMA packet transfer is not started (not requested).
31
30
29
28
27
26
25
24
SHRT_PCKT
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
BUSY_BANK
–
–
15
14
13
12
11
10
9
8
–
ERR_FLUSH
ERR_CRC_NT
R
ERR_FL_ISO TXRDY_TRER
TX_COMPLT
RXRDY_TXKL
ERR_OVFLW
7
6
5
4
3
2
1
0
MDATA_RX
DATAX_RX
–
–
INTDIS_DMA
–
AUTO_VALID
EPT_ENABL