Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
564
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
32.7.21 UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as described below:
Offset 0:
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: UDPHS_DMANXTDSCx
Offset 4:
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: UDPHS_DMAADDRESSx
Offset 8:
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: UDPHS_DMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following
pages).
pages).
Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor
is automatically loaded upon Endpointx request for packet transfer.
is automatically loaded upon Endpointx request for packet transfer.
32.7.22 UDPHS DMA Next Descriptor Address Register
Name:
UDPHS_DMANXTDSCx [x = 0..5]
Address:
0xF803C300 [0], 0xF803C310 [1], 0xF803C320 [2], 0xF803C330 [3], 0xF803C340 [4], 0xF803C350 [5]
Access:
Read-write
Note:
Channel 0 is not used.
• NXT_DSC_ADD: Next Descriptor Address
This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the
address must be equal to zero.
address must be equal to zero.
31
30
29
28
27
26
25
24
NXT_DSC_ADD
23
22
21
20
19
18
17
16
NXT_DSC_ADD
15
14
13
12
11
10
9
8
NXT_DSC_ADD
7
6
5
4
3
2
1
0
NXT_DSC_ADD