Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
573
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
33.5 Product Dependencies
33.5.1 I/O Lines
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed
physical transceivers are controlled by the USB host controller.
physical transceivers are controlled by the USB host controller.
One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device
is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
In the case the port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM, DHSDP and
DHSDM. The transceiver is automatically selected for Device operation once the USB High Speed Device is enabled.
DHSDM. The transceiver is automatically selected for Device operation once the USB High Speed Device is enabled.
In the case the port A is driven by the USB High Speed Host, the output signals are HFSDPA, HFSDMA, HHSDPA and
HHSDMA.
HHSDMA.
33.5.2 Power Management
The system embeds 2 transceivers.
The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock is provided
by the UTMI PLL, it is UPLLCK.
by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible. Nevertheless,
OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI.
OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be
generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV field.
generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV field.
Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral Clock
(MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the
bus USB signals (Recovered 12 MHz domain) in Full-speed operations.
(MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the
bus USB signals (Recovered 12 MHz domain) in Full-speed operations.
For High-speed operations, the user has to perform the following:
Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
Write CKGR_PLLCOUNT field in PMC_UCKR register.
Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB register.
Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9
(division by 10) if UPLLCK is selected.
(division by 10) if UPLLCK is selected.
Enable OHCI clocks, UHP bit in PMC_SCER register.
For OHCI Full-speed operations only, the user has to perform the following:
Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
Select PLLACK as Input clock of OHCI part, USBS bit in PMC_USB register.
Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to
calculated regarding the PLLACK value and USB Full-speed accuracy.
calculated regarding the PLLACK value and USB Full-speed accuracy.
Enable the OHCI clocks, UHP bit in PMC_SCER register.