Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
590
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
5.
Program HSMCI_DMA register with the following fields:
ROPT field is set to 0.
OFFSET field is set to 0.
CHKSIZE is user defined.
DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to
false.
false.
6.
Issue a READ_SINGLE_BLOCK command.
7.
Program the DMA controller.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
register.
3. Program the channel registers.
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO
address.
5. The DMAC_DADDRx register for Channel x must be word aligned.
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
7. Program the DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA controller is
able to prefetch data and write HSMCI simultaneously.
8. Program the DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
8.
Wait for XFRDONE in the HSMCI_SR register.
34.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)
In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB
access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to
copy exactly the block length number of bytes using 2 transfer descriptors.
access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to
copy exactly the block length number of bytes using 2 transfer descriptors.
1.
Use the previous step until READ_SINGLE_BLOCK then
2.
Program the DMA controller to use a two descriptors linked list.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
register.
3. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W, standing for LLI word oriented transfer.