Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
640
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
35.7.3.7 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to
NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode
Register (SPI_MR).
NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode
Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven
low.
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven
low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the
Mode Register or the Transmit Data Register (depending on PS).
Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.
transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the
characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded
peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible
peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded
peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible
peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
implementation.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled. This is
not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
Figure 35-9. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
35.7.3.8 Peripheral Deselection without DMA
During a transfer of more than one data on a Chip Select without the DMA, the SPI_TDR is loaded by the processor, the
flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is
detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer
and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted
between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt
or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep
the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will
give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select
line to remain active (low) during a full set of transfers might lead to communication errors.
flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is
detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer
and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted
between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt
or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep
the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will
give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select
line to remain active (low) during a full set of transfers might lead to communication errors.
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
1-of-n Decoder/Demultiplexer
MISO MOSI
NSS
Slave 0
SPCK MISO MOSI
NSS
Slave 1
SPCK MISO MOSI
NSS
Slave 14
NPCS3