Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

905

SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

CAN_BR

0xF8000014 (0), 0xF8004014 (1)

Read-write

This register can only be written if the WPEN bit is cleared in 

.

Any modification on one of the fields of the CAN_BR register must be done while CAN module is disabled.

To compute the different Bit Timings, please refer to the 

This phase is used to compensate the edge phase error.

Warning: PHASE2 value must be different from 0.

This phase is used to compensate for edge phase error.

This part of the bit time is used to compensate for the physical delay times within the network.

To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on 
any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit 
period may be shortened or lengthened by re-synchronization.

This field allows user to program the period of the CAN system clock to determine the individual bit timing.

The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.

0 (ONCE): The incoming bit stream is sampled once at sample point. 

1 (THREE): The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.

SMP Sampling Mode is automatically disabled if BRP = 0.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

SMP

23

22

21

20

19

18

17

16

–

BRP

15

14

13

12

11

10

9

8

–

–

SJW

–

PROPAG

7

6

5

4

3

2

1

0

–

PHASE1

–

PHASE2

t

PHS2

t

CSC

PHASE2

1

+

(

)

×

=

t

PHS1

t

CSC

PHASE1

1

+

(

)

×

=

t

PRS

t

CSC

PROPAG

1

+

(

)

×

=

t

SJW

t

CSC

SJW

1

+

(

)

×

=

t

CSC

BRP

1

+

(

) MCK

⁄

=