Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1212
Transmitted pause frames comprise the following:
A destination address of 01-80-C2-00-00-01
A source address taken from Specific Address Register 1
A type ID of 88-08 (MAC control frame)
A pause opcode of 01-01
A priority enable vector taken from Transmit PFC Pause Register
8 pause quantum registers
Fill of 00 to take the frame to minimum frame length
Valid FCS
The pause quantum registers used in the generated frame will depend on the trigger source for the frame as
follows:
follows:
If bit 17 of the Network Control Register is written with a one, then the priority enable vector of the priority-
based pause frame will be set equal to the value stored in the Transmit PFC Pause Register [7:0]. For each
entry equal to zero in the Transmit PFC Pause Register[15:8], the pause quantum field of the pause frame
associated with that entry will be taken from the transmit pause quantum register. For each entry equal to
one in the Transmit PFC Pause Register[15:8], the pause quantum associated with that entry will be zero.
based pause frame will be set equal to the value stored in the Transmit PFC Pause Register [7:0]. For each
entry equal to zero in the Transmit PFC Pause Register[15:8], the pause quantum field of the pause frame
associated with that entry will be taken from the transmit pause quantum register. For each entry equal to
one in the Transmit PFC Pause Register[15:8], the pause quantum associated with that entry will be zero.
The Transmit Pause Quantum Register resets to a value of 0xFFFF giving maximum pause quantum as
default.
default.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status Register)
and the only statistics register that will be incremented will be the Pause Frames Transmitted Register.
and the only statistics register that will be incremented will be the Pause Frames Transmitted Register.
PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods.
43.5.17 PHY Interface
Different PHY interfaces are supported by the Ethernet MAC:
MII
The MII interface is provided for 10/100 operation and uses txd[3:0] and rxd[3:0].
43.5.18 10/100 Operation
The 10/100 Mbps speed bit in the Network Configuration Register is used to select between 10 Mbps and 100
Mbps.
Mbps.
43.5.19 Jumbo Frames
The jumbo frames enable bit in the Network Configuration Register allows the GMAC, in its default configuration,
to receive jumbo frames up to 10240 bytes in size. This operation does not form part of the IEEE 802.3
specification and is normally disabled. When jumbo frames are enabled, frames received with a frame size greater
than 10240 bytes are discarded.
to receive jumbo frames up to 10240 bytes in size. This operation does not form part of the IEEE 802.3
specification and is normally disabled. When jumbo frames are enabled, frames received with a frame size greater
than 10240 bytes are discarded.