Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

Initialization of the GMAC configuration (e.g., loop back mode, frequency ratios) must be done while the transmit
and receive circuits are disabled. See the description of the Network Control Register and Network Configuration
Register earlier in this document.

To change loop back mode, the following sequence of operations must be followed:

1.

Write to Network Control Register to disable transmit and receive circuits.

2.

Write to Network Control Register to change loop back mode.

3.

Write to Network Control Register to re-enable transmit or receive circuits.

Note:

These writes to the Network Control Register cannot be combined in any way.

Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data
structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor
entries as defined in 

 The Receive Buffer Queue Pointer Register points to this data structure. 

To create the list of buffers:

1.

Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in 
the DMA Configuration Register.

2.

Allocate an area 8N bytes for the receive buffer descriptor list in system memory and create N entries in this 
list. Mark all entries in this list as owned by GMAC, i.e., bit 0 of word 0 set to 0.

3.

Mark the last descriptor in the queue with the wrap bit (bit 1 in word 0 set to 1).

4.

Write address of receive buffer descriptor list and control information to GMAC register receive buffer queue 
pointer

5.

The receive circuits can then be enabled by writing to the address recognition registers and the Network 
Control Register.

Receive Buffer Queue Pointer

(MAC Register)

Receive Buffer 0

Receive Buffer 1

Receive Buffer N

Receive Buffer Descriptor List

(In memory)

(In memory)