Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
587
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 30-2.
Master Clock Controller
30.5
Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the processor sleep mode. The
processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor
instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR).
processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor
instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR).
The processor clock HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
processor sleep mode is achieved by disabling the processor clock, which is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
processor sleep mode is achieved by disabling the processor clock, which is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
When processor sleep mode is entered, the current instruction is finished before the clock is stopped, but this does
not prevent data transfers from other masters of the system bus.
not prevent data transfers from other masters of the system bus.
30.6
SysTick Clock
The SysTick calibration value is fixed to 15000 which allows the generation of a time base of 1 ms with SysTick
clock to the maximum frequency on MCK divided by 8.
clock to the maximum frequency on MCK divided by 8.
30.7
USB Clock Controller
The user can select the PLLA output as the USB source clock by writing the USBS bit in PMC_USB. If using the
USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV bit in the
USB Clock register (PMC_USB).
USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV bit in the
USB Clock register (PMC_USB).
When the PLL output is stable, i.e., the LOCK bit is set:
the USB device clock can be enabled by setting the UDP bit in the System Clock Enable register
(PMC_SCER). To save power on this peripheral when it is not used, the user can set the UDP bit in the
System Clock Disable register (PMC_SCDR). The UDP bit in the System Clock Status register
(PMC_SCSR) gives the activity of this clock. The USB device port requires both the 48 MHz signal and the
master clock. The master clock may be controlled by means of the Master Clock Controller.
(PMC_SCER). To save power on this peripheral when it is not used, the user can set the UDP bit in the
System Clock Disable register (PMC_SCDR). The UDP bit in the System Clock Status register
(PMC_SCSR) gives the activity of this clock. The USB device port requires both the 48 MHz signal and the
master clock. The master clock may be controlled by means of the Master Clock Controller.
Figure 30-3.
USB Clock Controller
SLCK
Master Clock
Prescaler
MCK
PRES
CSS
MAINCK
PLLACK
To the Processor
Clock Controller (HCLK)
Clock Controller (HCLK)
PMC_MCKR
PMC_MCKR
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/3,.../16