Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral
Clock Controller. The user can individually enable and disable the clock on the peripherals.

The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0),
Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock
Disable 1 (PMC_PCDR1) registers. The status of the peripheral clock activity can be read in the Peripheral Clock
Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1).

When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.

To stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.

The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1, and
PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number corresponds to the
interrupt source number assigned to the peripheral.

The free-running processor clock (FCLK) used for sampling interrupts and clocking debug blocks ensures that
interrupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to
master clock (MCK).

The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently programmed
via the Programmable Clock Registers (PMC_PCKx).

PCKx can be independently selected between the slow clock (SLCK), the main clock (MAINCK), the PLLA clock
(PLLACK),and the master clock (MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be
divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. 

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR.

Moreover, like the PCK, a status bit in PMC_SR indicates that the programmable clock is actually what has been
programmed in the programmable clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the programmable clock before any configuration change and to re-enable it after the
change is actually performed.

The device allows the processor to restart in less than 10 microseconds while the device exits Wait Mode only if
the C-code function managing the wait mode entry and exit is linked to and executed from on-chip SRAM. 

The fast startup time cannot be achieved when the first instruction after an exit is located in the embedded Flash. If
fast startup is not required or if the first instruction after a wait mode exit is located in embedded Flash, see 

.

Prior to instructing the device to enter wait mode, the Fast RC oscillator must be selected as  the  master clock
source (the CSS field in PMC_MCKR must be written to 1) and the internal sources of wake-up must be cleared. It
must be verified that none of the enabled external wake-up inputs (WKUP) hold an active polarity.