Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
1036
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
47.5
Functional Description
As soon as the TRNG is enabled in the control register (TRNG_CR), the generator provides one 32-bit value every
84 clock cycles. Interrupt trng_int can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This
interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read. The
flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output data register
(TRNG_ODATA).
84 clock cycles. Interrupt trng_int can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This
interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read. The
flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output data register
(TRNG_ODATA).
The normal mode of operation checks that the status register flag equals 1 before reading the output data register when
a 32-bit random value is required by the software application.
a 32-bit random value is required by the software application.
Figure 47-2. TRNG Data Generation Sequence
84 clock cycles
84 clock cycles
84 clock cycles
Read TRNG_ISR
Read TRNG_ODATA
Read TRNG_ISR
Read TRNG_ODATA
Clock
trng_int
trng_cr
enable