Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

Product codes
AT91SAM9N12-EK
Page of 1104
1060
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
48.14 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
DDR2-400 limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
LP-DDR (1.8V, 30pF on data/control, 10pF on CK)
Tcyc = 5.0 ns, Fmax = 125 MHz
Tcyc = 6.0 ns, Fmax = 110 MHz
Tcyc = 7.5 ns, Fmax = 95 MHz
SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK)
SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK)
LP-SDR-133 (1.8V, 30 pF on data/control, 10 pF on CK)
48.15 Peripheral Timings
48.15.1 SPI 
48.15.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes.
Master Write Mode
The SPI only sends data to a slave device such as an LCD, for example. The limit is given by SPI
2
 (or SPI
5
) timing. 
Since it gives a maximum frequency above the maximum pad speed (see 
quency is the one from the pad.
Master Read Mode
T
valid 
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI DataFlash 
(AT45DB642D), T
valid
 (orT
) is 12 ns Max.
This gives, F
SPCK
Max = 47.1 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings 
SPI
7
/SPI
8
(or SPI
10
/SPI
11
). Since this gives a frequency well above the pad limit, the limit in slave read mode is 
given by SPCK pad.
Slave Write Mode
T
setup 
is the setup time from the master before sampling data (12ns).
This gives, F
SPCK
Max = 44.6 MHz @ VDDIO = 3.3V. 
f
SPCK
Max
1
SPI
0
orSPI
3
(
T
valid
+
--------------------------------------------------------
=
f
SPCK
Max
1
SPI
6
orSPI
9
(
T
setup
+
---------------------------------------------------------
=