Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

When a Reset (User reset, watchdog, software reset) occurs during SDRAM read access, the SDRAM clock is turned off
while data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.

This leads to a data bus conflict and adversely affects the boot memories connected on the EBI:



 NAND Flash boot functionality, if the system boots out of internal ROM.



 NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.

1.

Boot from Serial Flash or Data Flash on SPI

2.

Connect the NAND Flash on D16-D23 and set NFD0_ON_D16 to 1 in CCFG_EBICSA register. 
Warning! This prohibits connecting another device on the EBI.

When slow clock is selected as the source clock to feed PWM with (CLKPWMSEL in LCDC_LCDCFG0), the output
waveform generated is corrupted. When the MCK is selected the prescaler (PWMPS in LCDC_LCDCFG6) is not sized to
generate the PWM output in a range of 200 Hz - 1 kHz.

Use standalone PWM output instead of LCDC embedded PWM.

After power-up, the 12 MHz RC is enabled automatically. It is not enabled after a reset, even if it is used during the boot
process.

The user must not disable the 12 MHz RC to avoid any system freezing on reset event.

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