Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

120

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

RSTC_SR

0xFFFFFE04

Read-only

0: No high-to-low edge on NRST happened since the last read of RSTC_SR.

1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.  

Registers the NRST Pin Level at Master Clock (MCK).

0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 

1: A software reset command is being performed by the reset controller. The reset controller is busy.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

SRCMP

NRSTL

15

14

13

12

11

10

9

8

–

–

–

–

–

RSTTYP

7

6

5

4

3

2

1

0

–

–

–

–

–

–

–

URSTS

0

GENERAL_RST

Both VDDCORE and VDDBU rising

1

WKUP_RST

VDDCORE rising

2

WDT_RST

Watchdog fault occurred

3

SOFT_RST

Processor reset required by the software

4

USER_RST

NRST pin detected low